Searched refs:FMINNAN (Results 1 - 11 of 11) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 524 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
526 FMINNAN, FMAXNAN, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 1102 case ISD::FMINNAN:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 155 case ISD::FMINNAN: return "fminnan";
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| H A D | LegalizeVectorOps.cpp | 304 case ISD::FMINNAN:
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| H A D | LegalizeVectorTypes.cpp | 112 case ISD::FMINNAN:
672 case ISD::FMINNAN:
2036 case ISD::FMINNAN:
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| H A D | SelectionDAGBuilder.cpp | 2480 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2485 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT))
2486 Opc = ISD::FMINNAN;
2489 ISD::FMINNUM : ISD::FMINNAN;
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| H A D | LegalizeFloatTypes.cpp | 1872 case ISD::FMINNAN:
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| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 144 setOperationAction(ISD::FMINNAN, T, Legal);
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| /external/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 790 setOperationAction(ISD::FMINNAN, VT, Expand);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 307 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
399 setOperationAction(ISD::FMINNAN, Ty, Legal);
702 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
8405 return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1001 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
1003 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
1005 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
2856 ? ISD::FMINNAN : ISD::FMAXNAN;
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