/external/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 148 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) 149 if (Op0->getOpcode() == OpcodeToExpand) { 151 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; 207 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); 211 if (Op0 && Op0->getOpcode() == Opcode) { 212 Value *A = Op0->getOperand(0); 213 Value *B = Op0->getOperand(1); 253 if (Op0 529 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 585 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 661 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 778 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 788 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 830 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 866 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 894 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 957 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 966 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 975 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 984 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 994 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1080 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1088 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1098 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1106 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1114 SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned) argument 1148 SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1159 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1220 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1228 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1238 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1246 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1254 SimplifyFRemInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &, unsigned) argument 1273 SimplifyFRemInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1311 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1349 SimplifyRightShift(unsigned Opcode, Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1380 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 1397 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1407 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1421 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1432 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1455 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1507 SimplifyAndOfICmps(ICmpInst *Op0, ICmpInst *Op1) argument 1559 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1656 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1666 SimplifyOrOfICmps(ICmpInst *Op0, ICmpInst *Op1) argument 1718 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1844 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument 1854 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1901 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout &DL, const TargetLibraryInfo *TLI, const DominatorTree *DT, AssumptionCache *AC, const Instruction *CxtI) argument [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 177 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 182 if (Value *V = SimplifyMulInst(Op0, Op1, DL, TLI, DT, AC)) 190 BinaryOperator *BO = BinaryOperator::CreateNeg(Op0, I.getName()); 252 if (Op0->hasOneUse()) { 255 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) 257 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) 271 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) 275 if (isa<PHINode>(Op0)) 283 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { 293 if (Value *Op0v = dyn_castNegVal(Op0)) { // 536 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 790 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 960 foldUDivPow2Cst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 971 foldUDivNegCst(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 980 foldUDivShl(Value *Op0, Value *Op1, const BinaryOperator &I, InstCombiner &IC) argument 1003 visitUDivOperand(Value *Op0, Value *Op1, const BinaryOperator &I, SmallVectorImpl<UDivFoldAction> &Actions, unsigned Depth = 0) argument 1043 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1116 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1214 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1348 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1380 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1415 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1490 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineAndOrXor.cpp | 890 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 893 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); 1216 Value *Op0 = I.getOperand(0); local 1219 if (Value *Op0NotVal = dyn_castNotVal(Op0)) 1221 if (Op0->hasOneUse() && Op1->hasOneUse()) { 1233 if (match(Op0, m_OneUse(m_Xor(m_ZExt(m_Value(A)), m_ConstantInt(C1)))) && 1252 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1257 if (Value *V = SimplifyAndInst(Op0, Op1, DL, TLI, DT, AC)) 1276 if (BinaryOperator *Op0I = dyn_cast<BinaryOperator>(Op0)) { 1359 if (match(Op0, m_Trun 1883 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 2233 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2618 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2902 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local [all...] |
H A D | InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 33 if (isa<Constant>(Op0)) 39 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) 321 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, argument 339 CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this, &I)) { 341 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n"); 344 I, GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this, DL)); 349 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits(); 355 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0)) 362 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) [all...] |
H A D | InstCombineCompares.cpp | 2584 /// \brief Check if the order of \p Op0 and \p Op1 as operand in an ICmpInst 2591 /// \return true if Op0 and Op1 should be swapped. 2592 static bool swapMayExposeCSEOpportunities(const Value * Op0, argument 2596 if (Op0->getType()->isPointerTy()) 2598 // Count every uses of both Op0 and Op1 in a subtract. 2599 // Each time Op0 is the first operand, count -1: swapping is bad, the 2601 // Each time Op0 is the second operand, count +1: swapping is good, the 2603 // At the end, if the benefit is greater than 0, Op0 should come second to 2606 for (const User *U : Op0->users()) { 2610 // If Op0 i 2743 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 4088 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineAddSub.cpp | 1493 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1498 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(), 1508 BinaryOperator *Res = BinaryOperator::CreateAdd(Op0, V); 1524 return BinaryOperator::CreateXor(Op0, Op1); 1527 if (match(Op0, m_AllOnes())) 1530 if (Constant *C = dyn_cast<Constant>(Op0)) { 1560 if (ConstantInt *C = dyn_cast<ConstantInt>(Op0)) { 1594 if (match(Op1, m_Add(m_Specific(Op0), m_Value(Y))) || 1595 match(Op1, m_Add(m_Value(Y), m_Specific(Op0)))) 1599 if (match(Op0, m_Su 1692 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineCalls.cpp | 386 static Value *SimplifyX86extrq(IntrinsicInst &II, Value *Op0, argument 397 Constant *C0 = dyn_cast<Constant>(Op0); 448 Builder.CreateBitCast(Op0, ShufTy), 463 Value *Args[] = {Op0, CILength, CIIndex}; 479 static Value *SimplifyX86insertq(IntrinsicInst &II, Value *Op0, Value *Op1, argument 528 Value *SV = Builder.CreateShuffleVector(Builder.CreateBitCast(Op0, ShufTy), 535 Constant *C0 = dyn_cast<Constant>(Op0); 565 Value *Args[] = {Op0, Op1, CILength, CIIndex}; 1208 Value *Op0 = II->getArgOperand(0); local 1210 unsigned VWidth0 = Op0 1245 Value *Op0 = II->getArgOperand(0); local 1268 Value *Op0 = II->getArgOperand(0); local 1304 Value *Op0 = II->getArgOperand(0); local 1349 Value *Op0 = II->getArgOperand(0); local 1517 Value *Op0 = Builder->CreateBitCast(II->getArgOperand(0), local [all...] |
H A D | InstructionCombining.cpp | 201 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0)); local 206 if (Op0 && Op0->getOpcode() == Opcode) { 207 Value *A = Op0->getOperand(0); 208 Value *B = Op0->getOperand(1); 219 (!Op0 || (isa<BinaryOperator>(Op0) && Op0->hasNoSignedWrap()))) { 221 // the operands to Op0. 257 if (Op0 556 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); local 715 Value *Op0 = SO, *Op1 = ConstOperand; local 772 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 341 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 346 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 352 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 358 virtual unsigned fastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, 365 unsigned Op0, bool Op0IsKill, unsigned Op1, 373 unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, 394 const TargetRegisterClass *RC, unsigned Op0, 400 const TargetRegisterClass *RC, unsigned Op0, 406 const TargetRegisterClass *RC, unsigned Op0, 413 const TargetRegisterClass *RC, unsigned Op0, [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, argument 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 381 Scatterer Op0 = scatter(&I, I.getOperand(0)); local 383 assert(Op0.size() == NumElems && "Mismatched binary operation"); 388 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 409 Scatterer Op0 local 415 Value *Op0 = SI.getOperand(0); local 476 Scatterer Op0 = scatter(&CI, CI.getOperand(0)); local 496 Scatterer Op0 = scatter(&BCI, BCI.getOperand(0)); local 548 Scatterer Op0 = scatter(&SVI, SVI.getOperand(0)); local [all...] |
H A D | CorrelatedValuePropagation.cpp | 194 Value *Op0 = C->getOperand(0); local 203 auto *I = dyn_cast<Instruction>(Op0); 208 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, C); 346 Value *Op0 = C->getOperand(0); 351 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, At);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 422 unsigned Op0 = getRegForValue(I->getOperand(0)); local 423 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. 445 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 458 ISDOpcode, Op0, Op0IsKill, CF); 473 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); 1296 unsigned Op0 = getRegForValue(I->getOperand(0)); local 1297 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. 1310 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0); 1316 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 1511 const Value *Op0 local 1719 fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 1792 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 1813 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1837 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1865 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1887 fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 1931 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1973 fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 1987 fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 101 MachineOperand &Op0 = MI->getOperand(0); local 112 NewMI->addOperand(Op0); 144 MachineOperand &Op0 = MI->getOperand(0); local 156 NewMI->addOperand(Op0); 186 MachineOperand &Op0 = MI->getOperand(0); local 197 NewMI->addOperand(Op0); 223 MachineOperand &Op0 = MI->getOperand(0); local 233 NewMI->addOperand(Op0);
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H A D | HexagonSplitDouble.cpp | 671 MachineOperand &Op0 = MI->getOperand(0); local 673 assert(Op0.isReg() && Op1.isImm()); 678 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 699 MachineOperand &Op0 = MI->getOperand(0); local 702 assert(Op0.isReg()); 706 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 732 MachineOperand &Op0 = MI->getOperand(0); local 734 assert(Op0.isReg() && Op1.isReg()); 738 UUPairMap::const_iterator F = PairMap.find(Op0.getReg()); 753 MachineOperand &Op0 local 877 MachineOperand &Op0 = MI->getOperand(0); local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 295 // If Op0 is null, then Node is a constant that can be loaded using: 299 // If Op0 is nonnull, then Node can be implemented using: 301 // (Opcode (Opcode Op0 UpperVal) LowerVal) 302 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 414 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 417 SDValue Op0, uint64_t Op1) { 421 changeComponent(AM, IsBase, Op0); 440 SDValue Op0 = N.getOperand(0); local 443 unsigned Op0Code = Op0->getOpcode(); 449 return expandAdjDynAlloc(AM, IsBase, Op0); 416 expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1) argument 1004 SDValue Op0 = N->getOperand(I ^ 1); local 1032 splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, uint64_t UpperVal, uint64_t LowerVal) argument 1229 SDValue Op0 = Node->getOperand(0); local [all...] |
H A D | SystemZISelLowering.cpp | 45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {} 48 SDValue Op0, Op1; member in struct:__anon12753::Comparison 50 // The opcode that should be used to compare Op0 and Op1. 1564 if (!C.Op0.hasOneUse() || 1565 C.Op0.getOpcode() != ISD::LOAD || 1570 auto *Load = cast<LoadSDNode>(C.Op0); 1581 // Make sure that ConstOp1 is in range of C.Op0. 1615 if (C.Op0.getValueType() != MVT::i32 || 1617 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, 1655 if (C.Op0 [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 1140 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); local 1142 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 1150 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1155 moveToTop(Op0, I); // Move dead operand to TOS. 1156 TOS = Op0; 1166 duplicateToTop(Op0, Dest, I); 1167 Op0 = TOS = Dest; 1174 duplicateToTop(Op0, Dest, I); 1175 Op0 = TOS = Dest; 1181 assert((TOS == Op0 || TO 1237 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); local 1263 unsigned Op0 = getFPReg(MI->getOperand(0)); local [all...] |
/external/llvm/include/llvm/IR/ |
H A D | GetElementPtrTypeIterator.h | 128 gep_type_begin(Type *Op0, ArrayRef<T> A) { argument 129 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin()); 134 gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
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/external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
H A D | reduce.hpp | 157 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 162 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) 178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 182 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
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/external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
H A D | reduce.hpp | 71 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 75 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) 80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
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/external/llvm/lib/ExecutionEngine/ |
H A D | ExecutionEngine.cpp | 647 Constant *Op0 = CE->getOperand(0); local 651 GenericValue Result = getConstantValue(Op0); 660 GenericValue GV = getConstantValue(Op0); 666 GenericValue GV = getConstantValue(Op0); 672 GenericValue GV = getConstantValue(Op0); 679 GenericValue GV = getConstantValue(Op0); 685 GenericValue GV = getConstantValue(Op0); 690 GenericValue GV = getConstantValue(Op0); 705 GenericValue GV = getConstantValue(Op0); 721 GenericValue GV = getConstantValue(Op0); [all...] |
/external/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 568 Value *Op0 = CI->getArgOperand(0); local 580 Rep = Builder.CreateShuffleVector(Op0, Op1, ConstantVector::get(Idxs)); 585 Value *Op0 = CI->getArgOperand(0); local 626 Rep = Builder.CreateShuffleVector(Op0, Rep, ConstantVector::get(Idxs2)); 631 Value *Op0 = CI->getArgOperand(0); local 646 Value *UndefV = UndefValue::get(Op0->getType()); 647 Rep = Builder.CreateShuffleVector(Op0, UndefV, ConstantVector::get(Idxs)); 660 Value *Op0 = CI->getArgOperand(0); local 681 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVecto [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 390 SDValue Op0, Op1; local 395 if (!SelectADDRrr(Op, Op0, Op1)) 396 SelectADDRri(Op, Op0, Op1); 400 OutOps.push_back(Op0);
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/external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/ |
H A D | reduce.hpp | 186 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 191 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op) 207 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9> 211 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm); 212 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 214 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 216 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, 1486 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, argument 1490 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm); 1492 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm); 1501 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true); 2063 const Value *Op0 = I->getOperand(0); local 2067 if (!isTypeSupported(Op0 3835 emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3855 emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3865 emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 3901 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4008 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4129 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument 4559 const Value *Op0 = I->getOperand(0); local [all...] |