/external/boringssl/src/ssl/test/runner/curve25519/ |
H A D | cswap_amd64.s | 19 MOVQ 88(DI),R8 24 CMOVQEQ R8,CX 25 CMOVQEQ R9,R8 29 MOVQ R8,88(DI) 33 MOVQ 104(DI),R8 38 CMOVQEQ R8,CX 39 CMOVQEQ R9,R8 43 MOVQ R8,104(DI) 47 MOVQ 120(DI),R8 52 CMOVQEQ R8,C [all...] |
H A D | mul_amd64.s | 35 MOVQ AX,R8 41 ADDQ AX,R8 45 ADDQ AX,R8 82 ADDQ AX,R8 99 ADDQ AX,R8 139 SHLQ $13,R9:R8 140 ANDQ SI,R8 154 ADDQ DX,R8 155 MOVQ R8,DX 160 ANDQ SI,R8 [all...] |
H A D | ladderstep_amd64.s | 30 MOVQ 64(DI),R8 35 MOVQ R8,R12 45 ADDQ 104(DI),R8 55 MOVQ R8,80(SP) 69 MOVQ AX,R8 117 ADDQ AX,R8 122 ADDQ AX,R8 137 SHLQ $13,R9:R8 138 ANDQ DX,R8 139 ADDQ CX,R8 [all...] |
H A D | freeze_amd64.s | 30 MOVQ 24(DI),R8 48 ADDQ R12,R8 49 MOVQ R8,R12 51 ANDQ AX,R8 67 CMPQ AX,R8 77 SUBQ AX,R8 82 MOVQ R8,24(DI)
|
H A D | square_amd64.s | 31 MOVQ DX,R8 70 ADCQ DX,R8 79 ADCQ DX,R8 101 SHLQ $13,R8:CX 105 ADDQ R8,R9 121 MOVQ DX,R8 124 ANDQ SI,R8 139 MOVQ R8,8(DI)
|
/external/libhevc/decoder/arm/ |
H A D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 102 @//R8 - STRIDE V 138 @LDR R8,[sp,#52] 145 @SUB R12,R8,R3, LSR #1 @// v offset 153 ADD R8,R2,R9,LSL #2 @// rgb_next_row = rgb + rgb_stride 299 VST1.32 D14,[R8]! 300 VST1.32 D15,[R8]! 301 VST1.32 D20,[R8]! 302 VST1.32 D21,[R8]! 303 VST1.32 D16,[R8]! 304 VST1.32 D17,[R8]! [all...] |
/external/v8/test/unittests/interpreter/ |
H A D | bytecode-array-writer-unittest.cc | 161 /* 3 42 E> */ B(Star), R8(1), 165 /* 10 */ B(Star), R8(3), 166 /* 12 */ B(ForInPrepare), R8(4), 168 /* 15 */ B(Star), R8(7), 169 /* 17 63 S> */ B(ForInDone), R8(7), R8(6), 171 /* 22 */ B(ForInNext), R8(3), R8(7), R8(4), U8(1), 173 /* 29 */ B(Star), R8( [all...] |
H A D | bytecode-utils.h | 33 #define R8(i) static_cast<uint8_t>(REG_OPERAND(i)) macro
|
/external/llvm/lib/Target/BPF/ |
H A D | BPFFrameLowering.cpp | 38 SavedRegs.reset(BPF::R8);
|
/external/strace/linux/x86_64/ |
H A D | userent.h | 10 XLAT(8*R8),
|
/external/boringssl/src/ssl/test/runner/poly1305/ |
H A D | poly1305_arm.s | 24 MOVW R2, R8 33 AND R8, R2, R2 61 MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13) 68 MOVW 56(R0), R8 69 WORD $0xe1180008 // TST R8, R8 not working see issue 5921 110 ADD R12, R8, R8 121 MULALU R1, R8, (R11, g) 122 MULALU R0, R8, (R1 [all...] |
H A D | poly1305_amd64.s | 31 MOVL 0(CX),R8 41 ANDL $0X0FFFFFFF,R8 45 MOVL R8,104(SP) 78 MOVL 4(SI),R8 82 MOVL R8,112(SP) 103 MOVL 4(SI),R8 107 MOVL R8,112(SP) 429 MOVL 112(SP),R8 430 ADDL DI,R8 431 MOVQ R8,11 [all...] |
/external/kernel-headers/original/uapi/asm-x86/asm/ |
H A D | ptrace-abi.h | 42 #define R8 72 macro
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, 49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, 54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, 60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|
/external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
H A D | reduce.hpp | 138 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9> 140 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 156 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 159 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 177 template <typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 179 __device__ __forceinline__ void mergeShfl(const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 184 For<0, tuple_size<tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9> >::value>::mergeShfl(val, delta, width, op);
|
/external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/ |
H A D | reduce.hpp | 158 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9> 160 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 167 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9> 169 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 185 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 188 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 206 template <typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 208 __device__ __forceinline__ void mergeShfl(const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 213 For<0, tuple_size<tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9> >::value>::mergeShfl(val, delta, width, op);
|
/external/libunwind/src/x86_64/ |
H A D | unwind_i.h | 47 #define R8 8 macro
|
H A D | init.h | 57 c->dwarf.loc[R8] = REG_INIT_LOC(c, r8, R8);
|
H A D | Gregs.c | 113 case UNW_X86_64_R8: loc = c->dwarf.loc[R8]; break;
|
/external/opencv3/modules/core/include/opencv2/core/cuda/detail/ |
H A D | reduce.hpp | 138 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9> 140 const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 146 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9> 148 const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 167 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 170 const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 177 template <typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 179 __device__ __forceinline__ void mergeShfl(const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 184 For<0, thrust::tuple_size<thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9> >::value>::mergeShfl(val, delta, width, op);
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 41 case R8: case R9: case R10: case R11: case R12: 52 case R8: case R9: case R10: case R11: case R12:
|
H A D | Thumb1InstrInfo.cpp | 30 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 31 NopInst.addOperand(MCOperand::createReg(ARM::R8));
|
/external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
H A D | reduce.hpp | 70 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 73 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 79 const tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>&,
|
/external/valgrind/coregrind/m_sigframe/ |
H A D | sigframe-amd64-darwin.c | 93 SC2(__r8,R8); 121 SC2(R8,__r8);
|
/external/opencv3/modules/core/include/opencv2/core/cuda/ |
H A D | reduce.hpp | 65 typename R0, typename R1, typename R2, typename R3, typename R4, typename R5, typename R6, typename R7, typename R8, typename R9, 68 const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>& val, 74 const thrust::tuple<R0, R1, R2, R3, R4, R5, R6, R7, R8, R9>&,
|