Searched refs:RL (Results 1 - 25 of 41) sorted by relevance

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/external/compiler-rt/test/tsan/
H A Ddeadlock_detector_stress_test.cc129 void RL(size_t i) { function in class:LockTest
284 RL(0); L(1); RU(0); U(1);
285 L(1); RL(0); RU(0); U(1);
290 RL(2); RL(3); RU(2); RU(3);
291 RL(3); RL(2); RU(2); RU(3);
374 RL(000);
375 RL(100);
376 RL(20
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/external/clang/lib/StaticAnalyzer/Checkers/
H A DPaddingChecker.cpp79 const ASTRecordLayout &RL = ASTContext.getASTRecordLayout(RD); local
80 assert(llvm::isPowerOf2_64(RL.getAlignment().getQuantity()));
82 CharUnits BaselinePad = calculateBaselinePad(RD, ASTContext, RL);
85 CharUnits OptimalPad = calculateOptimalPad(RD, ASTContext, RL);
168 const ASTRecordLayout &RL) {
170 CharUnits Offset = ASTContext.toCharUnitsFromBits(RL.getFieldOffset(0));
177 auto FieldOffsetBits = RL.getFieldOffset(FD->getFieldIndex());
182 PaddingSum += RL.getSize() - Offset;
204 const ASTRecordLayout &RL) {
234 CharUnits NewOffset = ASTContext.toCharUnitsFromBits(RL
166 calculateBaselinePad(const RecordDecl *RD, const ASTContext &ASTContext, const ASTRecordLayout &RL) argument
202 calculateOptimalPad(const RecordDecl *RD, const ASTContext &ASTContext, const ASTRecordLayout &RL) argument
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/external/autotest/client/site_tests/firmware_TouchMTB/
H A Dtest_conf.py420 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
426 GV.RL: ('horizontal', 'from right to left',),
475 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
482 GV.RL: ('horizontal', 'from right to left',),
508 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
516 GV.RL: ('from right to left', 'below the stationary finger'),
721 variations=(GV.LR, GV.RL, GV.TB, GV.BT),
726 GV.RL: ('bottom edge', 'from right to left', 'above'),
744 variations=(GV.LR, GV.RL, GV.TB, GV.BT),
749 GV.RL
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H A Dfirmware_constants.py70 GV.RL = 'right_to_left'
85 GV.HORIZONTAL_DIRECTIONS = [GV.HORIZONTAL, GV.LR, GV.RL, GV.CL, GV.CR]
H A DtouchbotII_robot_wrapper.py127 GV.RL: (END, CENTER, START, CENTER),
150 GV.RL: -45,
165 GV.RL: (CENTER, BELOW_CENTER),
/external/clang/lib/CodeGen/
H A DCGObjCRuntime.cpp41 const ASTRecordLayout *RL; local
43 RL = &CGM.getContext().getASTObjCImplementationLayout(ID);
45 RL = &CGM.getContext().getASTObjCInterfaceLayout(Container);
60 assert(Index < RL->getFieldCount() && "Ivar is not inside record layout!");
62 return RL->getFieldOffset(Index);
H A DCGRecordLayoutBuilder.cpp713 CGRecordLayout *RL = local
717 RL->NonVirtualBases.swap(Builder.NonVirtualBases);
718 RL->CompleteObjectVirtualBases.swap(Builder.VirtualBases);
721 RL->FieldInfo.swap(Builder.Fields);
724 RL->BitFields.swap(Builder.BitFields);
732 RL->print(llvm::outs());
756 dyn_cast<llvm::StructType>(RL->getLLVMType());
767 unsigned FieldNo = RL->getLLVMFieldNo(FD);
781 const CGBitFieldInfo &Info = RL->getBitFieldInfo(FD);
782 llvm::Type *ElementTy = ST->getTypeAtIndex(RL
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H A DCGDebugInfo.cpp1244 const ASTRecordLayout &RL = CGM.getContext().getASTRecordLayout(RD); local
1267 BaseOffset = CGM.getContext().toBits(RL.getBaseClassOffset(Base));
1430 const ASTRecordLayout &RL = CGM.getContext().getASTRecordLayout(RD); local
1433 if (RL.getPrimaryBase())
1834 const ASTRecordLayout &RL = CGM.getContext().getASTObjCInterfaceLayout(ID); local
1877 FieldOffset = RL.getFieldOffset(FieldNo);
2378 const ASTRecordLayout &RL = CGM.getContext().getASTRecordLayout(RD); local
2379 if (const CXXRecordDecl *PBase = RL.getPrimaryBase()) {
/external/v8/tools/release/
H A Dtest_scripts.py279 def RL(text, cb=None): function
479 RL("Y"),
491 RL("n"),
502 RL("Y"),
636 RL(""), # Open editor.
829 expectations.append(RL("")) # Open editor.
847 expectations.append(RL("Y")) # Sanity check.
1241 RL("Y"), # Automatically add corresponding ports (ab34567, ab56789)?
1276 RL("Y"), # Automatically increment patch level?
1278 RL("reviewe
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/external/testng/src/main/java/org/testng/junit/
H A DJUnit4TestRunner.java79 core.addListener(new RL());
111 private class RL extends RunListener { class in class:JUnit4TestRunner
/external/llvm/include/llvm/ADT/
H A DImmutableSet.h516 TreeTy *RL = getLeft(R); local
519 if (getHeight(RR) >= getHeight(RL))
520 return createNode(createNode(L,V,RL), R, RR);
522 assert(!isEmpty(RL) && "RL cannot be empty because it has a height >= 1");
524 TreeTy *RLL = getLeft(RL);
525 TreeTy *RLR = getRight(RL);
527 return createNode(createNode(L,V,RLL), RL, createNode(RLR,R,RR));
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp525 SDValue LL, LH, RL, RH, CL, CH; local
528 GetSplitOp(N->getOperand(2), RL, RH);
541 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
547 SDValue LL, LH, RL, RH; local
550 GetSplitOp(N->getOperand(3), RL, RH);
553 N->getOperand(1), LL, RL, N->getOperand(4));
H A DTargetLowering.cpp2894 SDValue RL, SDValue RH) const {
2908 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2909 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2910 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2912 if (!LL.getNode() && !RL.getNode() &&
2915 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2928 RL);
2934 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2935 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2944 RL);
2892 expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL, SDValue LH, SDValue RL, SDValue RH) const argument
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H A DLegalizeIntegerTypes.cpp2115 SDValue LL, LH, RL, RH; local
2117 GetExpandedInteger(N->getOperand(1), RL, RH);
2118 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2128 SDValue LL, LH, RL, RH; local
2130 GetExpandedInteger(N->getOperand(1), RL, RH);
2132 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
H A DDAGCombiner.cpp2873 SDValue LL, LR, RL, RR, CC0, CC1;
2874 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2883 LR.getValueType(), LL, RL);
2891 LR.getValueType(), LL, RL);
2898 LR.getValueType(), LL, RL);
2905 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2919 if (LL == RR && LR == RL) {
2921 std::swap(RL, RR);
2923 if (LL == RL && LR == RR) {
3586 SDValue LL, LR, RL, R local
5206 SDValue Lo, Hi, LL, LH, RL, RH; local
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/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp676 SDValue LL, RL, AddendL, AddendH; local
679 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
693 AddendL, LL, RL);
701 AddendL, LL, RL);
712 AddendL, LL, RL);
715 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
/external/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp391 : RL(L), TRI(RI) {}
394 const OrderedRegisterList &RL;
400 OrderedRegisterList::const_iterator B = P.RL.begin(), E = P.RL.end();
H A DHexagonBitSimplify.cpp1621 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
1623 RL.Reg, RL.Sub, MRI);
/external/opencv/ml/src/
H A Dmlboost.cpp580 // RL - ... primary split sends to the right and the surrogate split sends to the left
584 double LL = 0, RL = 0, LR, RR; local
603 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value.
621 RL += w; RR -= w;
622 if( RL + LR > best_val && sorted[i].val + epsilon < sorted[i+1].val )
624 best_val = RL + LR;
645 // RL - ... primary split sends to the right and the surrogate split sends to the left
H A Dmltree.cpp2056 // RL - ... primary split sends to the right and the surrogate split sends to the left
2063 int LL = 0, RL = 0, LR, RR; local
2079 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value.
2095 RL++; RR--;
2096 if( RL + LR > _best_val && sorted[i].val + epsilon < sorted[i+1].val )
2098 best_val = RL + LR;
2107 double LL = 0, RL = 0, LR, RR; local
2128 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value.
2146 RL += w; RR -= w;
2147 if( RL
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/external/clang/lib/Sema/
H A DSemaStmtAsm.cpp667 const ASTRecordLayout &RL = Context.getASTRecordLayout(RT->getDecl());
669 CharUnits Result = Context.toCharUnitsFromBits(RL.getFieldOffset(i));
/external/opencv3/apps/traincascade/
H A Dold_ml_tree.cpp2546 // RL - ... primary split sends to the right and the surrogate split sends to the left
2553 int LL = 0, RL = 0, LR, RR; local
2569 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value.
2585 RL++; RR--;
2586 if( RL + LR > _best_val && values[i] + epsilon < values[i+1] )
2588 best_val = RL + LR;
2597 double LL = 0, RL = 0, LR, RR; local
2619 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value.
2637 RL += w; RR -= w;
2638 if( RL
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H A Dold_ml_boost.cpp668 // RL - ... primary split sends to the right and the surrogate split sends to the left
672 double LL = 0, RL = 0, LR, RR; local
691 // now iteratively compute LL, LR, RL and RR for every possible surrogate split value.
709 RL += w; RR -= w;
710 if( RL + LR > best_val && values[i] + epsilon < values[i+1] )
712 best_val = RL + LR;
742 // RL - ... primary split sends to the right and the surrogate split sends to the left
/external/clang/include/clang/AST/
H A DStmt.h1350 explicit ReturnStmt(SourceLocation RL) : ReturnStmt(RL, nullptr, nullptr) {} argument
1352 ReturnStmt(SourceLocation RL, Expr *E, const VarDecl *NRVOCandidate) argument
1353 : Stmt(ReturnStmtClass), RetLoc(RL), RetExpr((Stmt *)E),
/external/clang/lib/AST/
H A DExprConstant.cpp1886 const ASTRecordLayout *RL = nullptr) {
1887 if (!RL) {
1889 RL = &Info.Ctx.getASTRecordLayout(Derived);
1892 Obj.getLValueOffset() += RL->getBaseClassOffset(Base);
1939 const ASTRecordLayout *RL = nullptr) {
1940 if (!RL) {
1942 RL = &Info.Ctx.getASTRecordLayout(FD->getParent());
1946 LVal.Offset += Info.Ctx.toCharUnitsFromBits(RL->getFieldOffset(I));
7643 const ASTRecordLayout &RL = Info.Ctx.getASTRecordLayout(RD); local
7645 assert(i < RL
7665 const ASTRecordLayout &RL = Info.Ctx.getASTRecordLayout(RD); local
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