Searched refs:Src1RC (Results 1 - 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 357 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; local
360 Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
362 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
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| H A D | SIInstrInfo.cpp | 2721 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2725 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2729 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2743 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
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