| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 43 UXTX, enumerator in enum:llvm::AArch64_AM::ShiftExtendType
63 case AArch64_AM::UXTX: return "uxtx";
130 case 3: return AArch64_AM::UXTX;
157 case AArch64_AM::UXTX: return 3; break;
|
| /external/v8/src/arm64/ |
| H A D | disasm-arm64.cc | 144 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
146 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
1648 (instr->ExtendMode() == UXTX))) {
1680 // Extend mode UXTX is an alias for shift mode LSL here.
1681 if (!((ext == UXTX) && (shift == 0))) {
|
| H A D | assembler-arm64-inl.h | 365 // Extend modes SXTX and UXTX require a 64-bit register.
366 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
397 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
|
| H A D | constants-arm64.h | 342 UXTX = 3, enumerator in enum:v8::internal::Extend
|
| H A D | assembler-arm64.cc | 2503 case UXTX:
2576 // LSL is encoded in the option field as UXTX.
2578 ext = UXTX;
|
| H A D | simulator-arm64.cc | 996 case UXTX:
1611 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
|
| H A D | macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| H A D | AArch64InstPrinter.cpp | 1046 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1048 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1052 ExtType == AArch64_AM::UXTX) ||
|
| /external/v8/test/cctest/ |
| H A D | test-disasm-arm64.cc | 393 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4");
405 COMPARE(cmn(csp, Operand(xzr, UXTX, 3)), "cmn csp, xzr, lsl #3");
419 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4");
431 COMPARE(cmp(csp, Operand(xzr, UXTX, 3)), "cmp csp, xzr, lsl #3");
|
| H A D | test-assembler-arm64.cc | 570 __ Orr(x9, x0, Operand(x1, UXTX, 3));
667 __ Orn(x9, x0, Operand(x1, UXTX, 3));
736 __ And(x9, x0, Operand(x1, UXTX, 3));
877 __ Bic(x9, x0, Operand(x1, UXTX, 3));
1005 __ Eor(x9, x0, Operand(x1, UXTX, 3));
1074 __ Eon(x9, x0, Operand(x1, UXTX, 3));
4035 __ Adc(x13, x1, Operand(x2, UXTX, 4));
4047 __ Adc(x23, x1, Operand(x2, UXTX, 4));
8228 __ adds(xzr, x0, Operand(x1, UXTX));
8229 __ adds(xzr, x1, Operand(xzr, UXTX));
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1005 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
1013 // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
1015 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX;
1021 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
1583 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX;
2415 .Case("uxtx", AArch64_AM::UXTX)
|
| /external/vixl/src/vixl/a64/ |
| H A D | disasm-a64.cc | 158 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
160 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
3348 (instr->ExtendMode() == UXTX))) {
3380 // Extend mode UXTX is an alias for shift mode LSL here.
3381 if (!((ext == UXTX) && (shift == 0))) {
|
| H A D | macro-assembler-a64.cc | 798 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
1495 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
|
| H A D | assembler-a64.cc | 340 // Extend modes SXTX and UXTX require a 64-bit register.
341 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
372 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
4865 case UXTX:
4946 // LSL is encoded in the option field as UXTX.
4948 ext = UXTX;
|
| H A D | constants-a64.h | 279 UXTX = 3, enumerator in enum:vixl::Extend
|
| H A D | simulator-a64.cc | 373 case UXTX:
1067 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 508 UXTX, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
|
| /external/vixl/test/ |
| H A D | test-disasm-a64.cc | 392 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4");
404 COMPARE(cmn(sp, Operand(xzr, UXTX, 3)), "cmn sp, xzr, lsl #3");
418 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4");
430 COMPARE(cmp(sp, Operand(xzr, UXTX, 3)), "cmp sp, xzr, lsl #3");
|
| H A D | test-assembler-a64.cc | 561 __ Orr(x9, x0, Operand(x1, UXTX, 3));
655 __ Orn(x9, x0, Operand(x1, UXTX, 3));
722 __ And(x9, x0, Operand(x1, UXTX, 3));
860 __ Bic(x9, x0, Operand(x1, UXTX, 3));
984 __ Eor(x9, x0, Operand(x1, UXTX, 3));
1051 __ Eon(x9, x0, Operand(x1, UXTX, 3));
8126 __ Adc(x13, x1, Operand(x2, UXTX, 4));
8138 __ Adc(x23, x1, Operand(x2, UXTX, 4));
12666 __ adds(xzr, x0, Operand(x1, UXTX));
12667 __ adds(xzr, x1, Operand(xzr, UXTX));
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1286 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
|
| H A D | AArch64ISelDAGToDAG.cpp | 592 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
|