/external/compiler-rt/lib/builtins/ppc/ |
H A D | restFP.S | 17 // If the compiler wants to restore f27..f31, it does a "b restFP+52" 36 lfd f27,-40(r1)
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H A D | saveFP.S | 15 // If the compiler wants to save f27..f31, it does a "bl saveFP+52" 34 stfd f27,-40(r1)
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/external/compiler-rt/lib/tsan/rtl/ |
H A D | tsan_ppc_regs.h | 60 #define f27 27 macro
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/external/llvm/test/MC/ARM/ |
H A D | symbol-variants.s | 89 ldr r3, =f27(GOT_PREL) 91 @ CHECK: 70 R_ARM_GOT_PREL f27
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/external/llvm/test/MC/Mips/mips32/ |
H A D | valid.s | 62 div.d $f29,$f20,$f27 93 mfc1 $a3,$f27 98 mov.s $f2,$f27 105 movn.d $f27,$f21,$k0 129 neg.d $f27,$f18 137 round.w.s $f27,$f28
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/external/clang/test/CodeGen/ |
H A D | arm-arguments.c | 129 // APCS-GNU-LABEL: define i128 @f27() 135 // AAPCS: define arm_aapcscc void @f27({{.*}} noalias sret 141 _Complex double f27(void) {} function
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/external/llvm/test/MC/Mips/mips1/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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H A D | valid.s | 40 div.d $f29,$f20,$f27 61 mfc1 $a3,$f27 66 mov.s $f2,$f27 81 neg.d $f27,$f18
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/external/llvm/test/MC/Mips/mips2/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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H A D | valid.s | 54 div.d $f29,$f20,$f27 81 mfc1 $a3,$f27 86 mov.s $f2,$f27 101 neg.d $f27,$f18 108 round.w.s $f27,$f28
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/external/llvm/test/MC/Mips/mips3/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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H A D | invalid-mips4.s | 19 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips4/ |
H A D | invalid-mips5-wrong-error.s | 10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction 40 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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H A D | valid.s | 77 div.d $f29,$f20,$f27 147 mfc1 $a3,$f27 152 mov.s $f2,$f27 161 movn.d $f27,$f21,$k0 183 neg.d $f27,$f18 197 round.w.s $f27,$f28
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/external/llvm/test/MC/Mips/mips64r6/ |
H A D | invalid-mips5-wrong-error.s | 9 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction 42 nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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/external/libjpeg-turbo/simd/ |
H A D | jsimd_mips_dspr2_asm.h | 86 #define f27 $f27 macro
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/external/llvm/test/MC/Mips/ |
H A D | mips-reginfo-fp64.s | 58 # Read and write from/to $f26 and $f27
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/external/v8/test/mjsunit/es6/ |
H A D | block-let-crankshaft-sloppy.js | 33 f27, f28, f29, f30, f31, f32, f33]; 202 function f27() { function
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H A D | block-let-crankshaft.js | 35 f27, f28, f29, f30, f31, f32, f33]; 204 function f27() { function
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/external/llvm/test/MC/ELF/ |
H A D | cfi.s | 161 f27: label
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/external/llvm/test/MC/PowerPC/ |
H A D | ppc64-regs.s | 67 #CHECK: .cfi_offset f27, 524 184 .cfi_offset f27,524
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/external/llvm/test/MC/Mips/mips32r6/ |
H A D | invalid-mips32.s | 18 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips32r2/ |
H A D | valid.s | 66 div.d $f29,$f20,$f27 107 mfc1 $a3,$f27 113 mov.s $f2,$f27 120 movn.d $f27,$f21,$k0 147 neg.d $f27,$f18 169 round.w.s $f27,$f28
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/external/llvm/test/MC/Mips/mips32r3/ |
H A D | valid.s | 66 div.d $f29,$f20,$f27 107 mfc1 $a3,$f27 113 mov.s $f2,$f27 120 movn.d $f27,$f21,$k0 147 neg.d $f27,$f18 169 round.w.s $f27,$f28
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/external/llvm/test/MC/Mips/mips32r5/ |
H A D | valid.s | 66 div.d $f29,$f20,$f27 108 mfc1 $a3,$f27 114 mov.s $f2,$f27 121 movn.d $f27,$f21,$k0 148 neg.d $f27,$f18 170 round.w.s $f27,$f28
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