Searched refs:fsqrt (Results 1 - 25 of 43) sorted by relevance

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/external/valgrind/none/tests/ppc32/
H A Dtest_fx.stdout.exp2 fsqrt 0.000000e+00 -> 0.00000000000000e+00
3 fsqrt inf -> inf
4 fsqrt -inf -> nan
5 fsqrt nan -> nan
6 fsqrt nan -> nan
7 fsqrt -5.000000e+100 -> nan
8 fsqrt -5.000000e+20 -> nan
9 fsqrt -5.010000e+02 -> nan
10 fsqrt -6.000000e+00 -> nan
11 fsqrt
[all...]
H A Djm-fp.stdout.exp846 fsqrt 0010000000000001 => 2000000000000000
847 fsqrt 00100094e0000359 => 2000004a6f52dd4a
848 fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
849 fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
850 fsqrt 8010000000000001 => 7ff8000000000000
851 fsqrt 80100094e0000359 => 7ff8000000000000
852 fsqrt bfe0000000000001 => 7ff8000000000000
853 fsqrt bfe00094e0000359 => 7ff8000000000000
854 fsqrt 0000000000000000 => 0000000000000000
855 fsqrt 800000000000000
[all...]
/external/llvm/test/MC/Mips/msa/
H A Dtest_2rf.s25 # CHECK: fsqrt.w $w0, $w11 # encoding: [0x7b,0x26,0x58,0x1e]
26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde]
58 fsqrt.w $w0, $w11
59 fsqrt.d $w15, $w12
/external/llvm/test/MC/AArch64/
H A Dfullfp16-neon-neg.s28 fsqrt.4h v0, v0
52 fsqrt.8h v0, v0
378 fsqrt v4.4h, v0.4h
380 fsqrt v6.8h, v8.8h
H A Dneon-simd-misc.s730 fsqrt v4.4h, v0.4h
731 fsqrt v6.8h, v8.8h
732 fsqrt v6.4s, v8.4s
733 fsqrt v6.2d, v8.2d
734 fsqrt v4.2s, v0.2s
736 // CHECK: fsqrt v4.4h, v0.4h // encoding: [0x04,0xf8,0xf9,0x2e]
737 // CHECK: fsqrt v6.8h, v8.8h // encoding: [0x06,0xf9,0xf9,0x6e]
738 // CHECK: fsqrt v6.4s, v8.4s // encoding: [0x06,0xf9,0xa1,0x6e]
739 // CHECK: fsqrt v6.2d, v8.2d // encoding: [0x06,0xf9,0xe1,0x6e]
740 // CHECK: fsqrt v
[all...]
H A Darm64-fp-encoding.s146 fsqrt h1, h2
147 fsqrt s1, s2
148 fsqrt d1, d2
150 ; FP16: fsqrt h1, h2 ; encoding: [0x41,0xc0,0xe1,0x1e]
152 ; NO-FP16-NEXT: fsqrt h1, h2
153 ; CHECK: fsqrt s1, s2 ; encoding: [0x41,0xc0,0x21,0x1e]
154 ; CHECK: fsqrt d1, d2 ; encoding: [0x41,0xc0,0x61,0x1e]
H A Darm64-advsimd.s585 fsqrt.2s v0, v0
635 ; CHECK: fsqrt.2s v0, v0 ; encoding: [0x00,0xf8,0xa1,0x2e]
682 fsqrt.4h v0, v0
695 ; CHECK: fsqrt.4h v0, v0 ; encoding: [0x00,0xf8,0xf9,0x2e]
708 fsqrt.8h v0, v0
721 ; CHECK: fsqrt.8h v0, v0 ; encoding: [0x00,0xf8,0xf9,0x6e]
H A Dneon-diagnostics.s5973 fsqrt v0.16b, v31.16b
5974 fsqrt v2.8h, v4.8h
5975 fsqrt v1.8b, v9.8b
5976 fsqrt v13.4h, v21.4h
6261 // CHECK-ERROR: fsqrt v0.16b, v31.16b
6264 // CHECK-ERROR: fsqrt v2.8h, v4.8h
6267 // CHECK-ERROR: fsqrt v1.8b, v9.8b
6270 // CHECK-ERROR: fsqrt v13.4h, v21.4h
H A Dbasic-a64-instructions.s1830 fsqrt s6, s7
1843 // CHECK: fsqrt s6, s7 // encoding: [0xe6,0xc0,0x21,0x1e]
1857 fsqrt d6, d7
1870 // CHECK: fsqrt d6, d7 // encoding: [0xe6,0xc0,0x61,0x1e]
/external/llvm/test/MC/PowerPC/
H A Dppc64-encoding-fp.s154 # CHECK-BE: fsqrt 2, 3 # encoding: [0xfc,0x40,0x18,0x2c]
155 # CHECK-LE: fsqrt 2, 3 # encoding: [0x2c,0x18,0x40,0xfc]
156 fsqrt 2, 3
157 # CHECK-BE: fsqrt. 2, 3 # encoding: [0xfc,0x40,0x18,0x2d]
158 # CHECK-LE: fsqrt. 2, 3 # encoding: [0x2d,0x18,0x40,0xfc]
159 fsqrt. 2, 3
/external/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-msa.s37 fsqrt.d $w3,$w1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
38 fsqrt.w $w5,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/valgrind/none/tests/ppc64/
H A Djm-fp.stdout.exp846 fsqrt 0010000000000001 => 2000000000000000
847 fsqrt 00100094e0000359 => 2000004a6f52dd4a
848 fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
849 fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
850 fsqrt 8010000000000001 => 7ff8000000000000
851 fsqrt 80100094e0000359 => 7ff8000000000000
852 fsqrt bfe0000000000001 => 7ff8000000000000
853 fsqrt bfe00094e0000359 => 7ff8000000000000
854 fsqrt 0000000000000000 => 0000000000000000
855 fsqrt 800000000000000
[all...]
/external/valgrind/auxprogs/
H A Dppcfround.c248 INSN(fsqrt, "fsqrt %%f4, %%f1");
249 INSN(fsqrt_, "fsqrt. %%f4, %%f1");
532 //do_N_unary(fsqrt, SHOW_ALL);
/external/opencv/cvaux/src/
H A Dcvtrifocal.cpp2755 eig[0] = fsqrt(cvmGet(&matrW,0,0));
2756 eig[1] = fsqrt(cvmGet(&matrW,1,1));
2757 eig[2] = fsqrt(cvmGet(&matrW,2,2));
/external/v8/src/ppc/
H A Dcodegen-ppc.cc35 __ fsqrt(d1, d1);
H A Dassembler-ppc.h1092 void fsqrt(const DoubleRegister frt, const DoubleRegister frb,
/external/v8/src/x87/
H A Dcodegen-x87.cc49 __ fsqrt();
H A Dassembler-x87.h891 void fsqrt();
H A Dassembler-x87.cc1736 void Assembler::fsqrt() { function in class:v8::internal::Assembler
/external/v8/test/cctest/
H A Dtest-disasm-arm64.cc1410 COMPARE(fsqrt(s8, s9), "fsqrt s8, s9");
1411 COMPARE(fsqrt(s31, s30), "fsqrt s31, s30");
1412 COMPARE(fsqrt(d10, d11), "fsqrt d10, d11");
1413 COMPARE(fsqrt(d31, d30), "fsqrt d31, d30");
/external/mesa3d/src/mesa/x86/
H A Dassyntax.h767 #define FSQRT CHOICE(fsqrt, fsqrt, fsqrt)
1488 #define FSQRT fsqrt
/external/v8/src/arm64/
H A Dmacro-assembler-arm64-inl.h858 fsqrt(fd, fn);
H A Dassembler-arm64.h1581 void fsqrt(const FPRegister& fd, const FPRegister& fn);
/external/v8/src/compiler/x87/
H A Dcode-generator-x87.cc1181 __ fsqrt();
1594 __ fsqrt();
/external/v8/src/compiler/ppc/
H A Dcode-generator-ppc.cc1317 ASSEMBLE_FLOAT_UNOP_RC(fsqrt, MiscField::decode(instr->opcode()));

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