Searched refs:getOpcode (Results 1 - 25 of 672) sorted by relevance

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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/iface/instruction/
H A DInstruction.java49 Opcode getOpcode(); method in interface:Instruction
/external/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h35 return Info->get(Inst.getOpcode()).isBranch();
39 return Info->get(Inst.getOpcode()).isConditionalBranch();
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
47 return Info->get(Inst.getOpcode()).isIndirectBranch();
51 return Info->get(Inst.getOpcode()).isCall();
55 return Info->get(Inst.getOpcode()).isReturn();
59 return Info->get(Inst.getOpcode()).isTerminator();
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/
H A DUnresolvedOdexInstruction.java52 @Override public Opcode getOpcode() { method in class:UnresolvedOdexInstruction
53 return originalInstruction.getOpcode();
/external/dexmaker/src/dx/java/com/android/dx/dex/code/
H A DFixedSizeInsn.java53 return getOpcode().getFormat().codeSize();
59 getOpcode().getFormat().writeTo(out, this);
71 return getOpcode().getFormat().listingString(this, noteIndices);
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp68 switch (I->getOpcode()) {
75 return selectOperator(I, I->getOpcode());
H A DWebAssemblyRegStackify.cpp96 if (Def->getOpcode() == TargetOpcode::PHI)
140 if (Insert->getOpcode() == TargetOpcode::PHI)
145 if (Insert->getOpcode() == TargetOpcode::INLINEASM)
174 if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF)
179 if (Def->getOpcode() == TargetOpcode::INLINEASM)
183 if (Def->getOpcode() == TargetOpcode::PHI)
188 if (Def->getOpcode() == WebAssembly::ARGUMENT_I32 ||
189 Def->getOpcode() == WebAssembly::ARGUMENT_I64 ||
190 Def->getOpcode() == WebAssembly::ARGUMENT_F32 ||
191 Def->getOpcode()
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/external/llvm/lib/MC/
H A DMCInstrAnalysis.cpp16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
H A DMCInst.cpp45 OS << "<MCInst " << getOpcode();
55 OS << "<MCInst #" << getOpcode();
59 OS << ' ' << Printer->getOpcodeName(getOpcode());
/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DNormalSsaInsn.java128 public Rop getOpcode() { method in class:NormalSsaInsn
129 return insn.getOpcode();
143 if (insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) {
180 return insn.getOpcode().getOpcode() == RegOps.MOVE;
186 return insn.getOpcode().getOpcode() == RegOps.MOVE_EXCEPTION;
218 Rop opcode = getOpcode();
227 switch (opcode.getOpcode()) {
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/external/llvm/lib/Target/AMDGPU/
H A DR600EmitClauseMarkers.cpp42 switch (MI->getOpcode()) {
56 if (TII->isLDSRetInstr(MI->getOpcode()))
60 TII->isCubeOp(MI->getOpcode()) ||
61 TII->isReductionOp(MI->getOpcode()))
75 if (TII->isALUInstr(MI->getOpcode()))
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
79 switch (MI->getOpcode()) {
93 switch (MI->getOpcode()) {
122 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() !
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/external/llvm/include/llvm/IR/
H A DOperator.h48 unsigned getOpcode() const { function in class:llvm::Operator
50 return I->getOpcode();
51 return cast<ConstantExpr>(this)->getOpcode();
56 static unsigned getOpcode(const Value *V) { function in class:llvm::Operator
58 return I->getOpcode();
60 return CE->getOpcode();
107 return I->getOpcode() == Instruction::Add ||
108 I->getOpcode() == Instruction::Sub ||
109 I->getOpcode() == Instruction::Mul ||
110 I->getOpcode()
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H A DInstruction.h104 /// getOpcode() returns a member of one of the enums like Instruction::Add.
105 unsigned getOpcode() const { return getValueID() - InstructionVal; } function in class:llvm::Instruction
107 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); }
108 bool isTerminator() const { return isTerminator(getOpcode()); }
109 bool isBinaryOp() const { return isBinaryOp(getOpcode()); }
110 bool isShift() { return isShift(getOpcode()); }
111 bool isCast() const { return isCast(getOpcode()); }
112 bool isFuncletPad() const { return isFuncletPad(getOpcode()); }
132 return getOpcode() == Shl || getOpcode()
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/external/llvm/lib/Target/PowerPC/
H A DPPCBranchSelector.cpp143 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
145 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
148 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
149 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
188 if (I->getOpcode() == PPC::BCC) {
199 } else if (I->getOpcode() == PPC::BC) {
202 } else if (I->getOpcode()
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H A DPPCEarlyReturn.cpp66 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
82 if (J->getOpcode() == PPC::B) {
86 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
94 } else if (J->getOpcode() == PPC::BCC) {
108 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
114 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
/external/dexmaker/src/dx/java/com/android/dx/rop/code/
H A DPlainInsn.java92 return new PlainInsn(getOpcode(), getPosition(),
115 Rop newRop = Rops.ropFor(getOpcode().getOpcode(), getResult(),
130 int opcode = getOpcode().getOpcode();
152 return new PlainInsn(getOpcode(), getPosition(),
H A DThrowingCstInsn.java84 return new ThrowingCstInsn(getOpcode(), getPosition(),
92 return new ThrowingCstInsn(getOpcode(), getPosition(),
103 return new ThrowingCstInsn(getOpcode(), getPosition(),
H A DThrowingInsn.java99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
/external/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp132 if (II->getOpcode() == TargetOpcode::KILL)
182 if (MII->getOpcode() == Hexagon::J2_call)
196 if (MII->getOpcode() == TargetOpcode::KILL ||
197 MII->getOpcode() == TargetOpcode::PHI ||
198 MII->getOpcode() == TargetOpcode::COPY)
205 if (MII->getOpcode() == Hexagon::LDriw_pred ||
206 MII->getOpcode() == Hexagon::STriw_pred)
230 ((MI->getOpcode() == Hexagon::C2_cmpeqi ||
231 MI->getOpcode() == Hexagon::C2_cmpgti) &&
248 if (def->getOpcode()
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/external/llvm/unittests/Transforms/Utils/
H A DIntegerDivision.cpp42 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv);
47 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
50 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub);
72 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv);
77 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp);
80 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI);
102 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem);
107 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
110 EXPECT_TRUE(Remainder && Remainder->getOpcode() == Instruction::Sub);
132 EXPECT_TRUE(BB->front().getOpcode()
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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/
H A DInstructionWriter.java99 writer.write(getOpcodeValue(instruction.getOpcode()));
108 writer.write(getOpcodeValue(instruction.getOpcode()));
117 writer.write(getOpcodeValue(instruction.getOpcode()));
126 writer.write(getOpcodeValue(instruction.getOpcode()));
135 writer.write(getOpcodeValue(instruction.getOpcode()));
144 writer.write(getOpcodeValue(instruction.getOpcode()));
154 writer.write(getOpcodeValue(instruction.getOpcode()));
164 writer.write(getOpcodeValue(instruction.getOpcode()));
174 writer.write(getOpcodeValue(instruction.getOpcode()));
184 writer.write(getOpcodeValue(instruction.getOpcode()));
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/external/dexmaker/src/dx/java/com/android/dx/io/instructions/
H A DZeroRegisterDecodedInstruction.java41 getFormat(), getOpcode(), newIndex, getIndexType(),
/external/llvm/lib/Target/NVPTX/
H A DNVPTXPeephole.cpp78 if (Root.getOpcode() != NVPTX::cvta_to_local_yes_64 &&
79 Root.getOpcode() != NVPTX::cvta_to_local_yes)
91 (GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 &&
92 GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) {
113 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
/external/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp119 (MI->getOpcode() == SP::RESTORErr
120 || MI->getOpcode() == SP::RESTOREri)) {
128 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
129 || MI->getOpcode() == SP::FCMPQ)) {
180 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
183 if (slot->getOpcode() == SP::RETL) {
187 if (J->getOpcode() == SP::RESTORErr
188 || J->getOpcode()
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp91 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
92 if (MI.getOpcode() == AMDGPU::RETURN ||
93 MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
94 MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
95 MI.getOpcode() == AMDGPU::BUNDLE ||
96 MI.getOpcode() == AMDGPU::KILL) {
170 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
/external/llvm/lib/Target/AArch64/
H A DAArch64BranchRelaxation.cpp302 switch (MI->getOpcode()) {
355 assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!");
385 BMI->getOpcode() == AArch64::B) {
395 getBranchDisplacementBits(MI->getOpcode()))) {
399 unsigned OpNum = (MI->getOpcode() == AArch64::TBZW ||
400 MI->getOpcode() == AArch64::TBNZW ||
401 MI->getOpcode() == AArch64::TBZX ||
402 MI->getOpcode() == AArch64::TBNZX)
406 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode())));
407 if (MI->getOpcode()
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