Searched refs:i64 (Results 1 - 25 of 154) sorted by relevance

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/external/valgrind/none/tests/s390x/
H A Drounding-5.c11 volatile int64_t i64; variable
49 __asm__ volatile("cegbr %[r1],%[r2]" : [r1] "=f"(out) : [r2] "d"(i64));
50 printf("cegbr: %"PRId64" -> %f\n", i64, out);
59 __asm__ volatile("cdgbr %[r1],%[r2]" : [r1] "=f"(out) : [r2] "d"(i64));
60 printf("cegbr: %"PRId64" -> %f\n", i64, out);
76 /* i64 -> f32 */
77 i64 = INT64_MAX;
80 i64 = INT64_MIN;
84 /* i64 -> f64 */
85 i64
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/external/clang/test/CodeGen/
H A Darm-microsoft-intrinsics.c29 __INT64_TYPE__ i64; local
30 return __ldrexd(&i64);
/external/valgrind/drd/tests/
H A Dannotate_trace_memory.c10 volatile int64_t i64; variable
19 DRD_TRACE_VAR(i64);
37 i64 = 9;
38 i64 += 0x12345678ULL;
45 DRD_STOP_TRACING_VAR(i64);
/external/valgrind/none/tests/arm64/
H A Dcvtf_imm.c11 typedef union { double d64; float f32[2]; unsigned long long int i64; } U; member in union:__anon20703
17 U block[2]; block[0].i64 = x; block[1].i64 = 0;
25 U block[2]; block[0].i64 = x; block[1].i64 = 0;
33 U block[2]; block[0].i64 = x; block[1].i64 = 0;
42 U block[2]; block[0].i64 = x; block[1].i64 = 0;
50 U block[2]; block[0].i64
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/external/boringssl/src/crypto/curve25519/asm/
H A Dx25519-asm-arm.S79 vmov.i64 q2,#0xffffffff
116 vadd.i64 q12,q4,q1
117 vadd.i64 q13,q10,q1
120 vadd.i64 q5,q5,q12
121 vshl.i64 q12,q12,#26
122 vadd.i64 q14,q5,q0
123 vadd.i64 q11,q11,q13
124 vshl.i64 q13,q13,#26
125 vadd.i64 q15,q11,q0
126 vsub.i64 q
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/external/clang/test/SemaCXX/
H A Dms_integer_suffix.cpp19 static_assert(sizeof(0i64) == __SIZEOF_INT64__, "");
/external/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp62 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
63 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64);
79 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
83 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
89 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64);
107 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
111 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
145 SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64);
H A DBPFISelLowering.cpp96 addRegisterClass(MVT::i64, &BPF::GPRRegClass);
103 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
107 setOperationAction(ISD::SETCC, MVT::i64, Expand);
108 setOperationAction(ISD::SELECT, MVT::i64, Expand);
109 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
111 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
113 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
118 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
119 setOperationAction(ISD::SREM, MVT::i64, Expan
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/external/libyuv/files/unit_test/
H A Dbasictypes_test.cc33 int64 i64 = -1; local
41 EXPECT_EQ(8u, sizeof(i64));
49 EXPECT_GT(0, i64);
/external/libhevc/common/arm/
H A Dihevc_intra_pred_luma_vert.s193 vmov.i64 d18, #0x00000000000000ff
201 vmov.i64 d19, d17
208 vmov.i64 d10, #0x00000000000000ff
219 vmov.i64 d11, d17
224 vmov.i64 d8, #0x00000000000000ff
225 vmov.i64 d9, d17
227 vmov.i64 d6, #0x00000000000000ff
228 vmov.i64 d7, d17
248 vmov.i64 d18, #0x00000000000000ff
249 @vmov.i64 d1
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H A Dihevc_intra_pred_chroma_mode2.s256 vshl.i64 d0,d12,#32
258 vshl.i64 d1,d13,#32
262 vshl.i64 d2,d14,#32
265 vshl.i64 d3,d15,#32
271 vshl.i64 d4,d16,#32
273 vshl.i64 d5,d17,#32
281 vshl.i64 d6,d18,#32
284 vshl.i64 d7,d19,#32
H A Dihevc_intra_pred_luma_dc.s132 vshl.i64 d8, d8, #32
201 vadd.i64 d14, d13, d28 @src[2nt+1]+2+src[2nt-1]+2dc_val
207 vadd.i64 d11, d13, d9 @3*dc
210 vadd.i64 d11, d11, d17 @3*dc + 2
240 vmov.i64 d19, #0x00000000000000ff @
251 vmov.i64 d20, #0x00000000000000ff @byte mask row 1 (prol)
257 vmov.i64 d21, #0x00000000000000ff @byte mask row 2 (prol)
266 vmov.i64 d20, #0x00000000000000ff @byte mask row 3 (prol)
274 vmov.i64 d21, #0x00000000000000ff @byte mask row 4 (prol)
282 vmov.i64 d2
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/external/dbus/dbus/
H A Ddbus-types.h166 dbus_int64_t i64; /**< as int64 */ member in union:__anon3683
/external/clang/test/Sema/
H A Dformat-strings-ms.c11 void non_iso_warning_test(__int32 i32, __int64 i64, wchar_t c, void *p) { argument
14 printf("%I64d", i64); // expected-warning{{'I64' length modifier is not supported by ISO C}}
/external/ltrace/sysdeps/linux-gnu/ppc/
H A Dfetch.c191 uint64_t i64; member in union:__anon13356
199 u.i64 = u.i32;
203 u.i8 = u.i64;
206 u.i16 = u.i64;
209 u.i32 = u.i64;
236 uint64_t i64; member in union:__anon13357
240 u.i64 = read_gpr(ctx, proc, reg_num);
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp134 BusyRegs.push_back(convReg(AddressReg, MVT::i64));
135 BusyRegs.push_back(convReg(ShadowReg, MVT::i64));
136 BusyRegs.push_back(convReg(ScratchReg, MVT::i64));
153 BusyRegs.push_back(convReg(Reg, MVT::i64));
240 assert(VT == MVT::i32 || VT == MVT::i64);
768 return getX86SubSuperRegister(FrameReg, MVT::i64);
794 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
815 SpillReg(Out, RegCtx.ShadowReg(MVT::i64));
816 SpillReg(Out, RegCtx.AddressReg(MVT::i64));
817 if (RegCtx.ScratchReg(MVT::i64) !
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/external/boringssl/src/crypto/modes/asm/
H A Dghash-armv4.pl375 vmov.i64 $t3#hi, #0
401 vshl.i64 $t0#hi,#57
406 vshl.i64 $IN,$IN,#1
422 vmov.i64 $k48,#0x0000ffffffffffff
424 vmov.i64 $k32,#0x00000000ffffffff
428 vmov.i64 $k16,#0x000000000000ffff
441 vmov.i64 $k48,#0x0000ffffffffffff
443 vmov.i64 $k32,#0x00000000ffffffff
447 vmov.i64 $k16,#0x000000000000ffff
472 vshl.i64
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/external/llvm/test/MC/ARM/
H A Dneon-sub-encoding.s6 vsub.i64 d16, d17, d16
11 vsub.i64 q8, q8, q9
17 vsub.i64 d16, d24
22 vsub.i64 q4, q7
28 @ CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3]
33 @ CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3]
39 @ CHECK: vsub.i64 d16, d16, d24 @ encoding: [0xa8,0x08,0x70,0xf3]
44 @ CHECK: vsub.i64 q4, q4, q7 @ encoding: [0x4e,0x88,0x38,0xf3]
127 @ CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2]
128 vsubhn.i64 d1
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/external/boringssl/src/crypto/poly1305/
H A Dpoly1305_arm_asm.S210 # asm 1: vmov.i64 >mask=reg128#7,#0xffffffff
211 # asm 2: vmov.i64 >mask=q6,#0xffffffff
212 vmov.i64 q6,#0xffffffff
215 # asm 1: vmov.i64 >u4=reg128#8,#0xff
216 # asm 2: vmov.i64 >u4=q7,#0xff
217 vmov.i64 q7,#0xff
270 # asm 1: vshl.i64 >u4=reg128#8,<u4=reg128#8,#24
271 # asm 2: vshl.i64 >u4=q7,<u4=q7,#24
272 vshl.i64 q7,q7,#24
954 # asm 1: vadd.i64 >r
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/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp298 case MVT::i64: // fall-through
313 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 &&
337 if (VT > MVT::i64)
344 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
346 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1000 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1005 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1011 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1015 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1019 ResultReg = emitLSL_ri(MVT::i64, MV
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/external/boringssl/src/crypto/sha/asm/
H A Dsha512-armv4.pl525 vadd.i64 $a,$Maj @ h+=Maj from the past
542 vadd.i64 $T1,$Ch,$h
545 vadd.i64 $T1,$t2
547 vadd.i64 $K,@X[$i%16]
552 vadd.i64 $T1,$K
555 vadd.i64 $d,$T1
556 vadd.i64 $Maj,$T1
557 @ vadd.i64 $h,$Maj
575 vadd.i64 @_[0],d30 @ h+=Maj from the past
584 vadd.i64
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/external/mesa3d/src/egl/main/
H A Deglcompiler.h57 # define INT64_C(__val) __val##i64
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp180 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
243 LocVT = MVT::i64;
252 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
407 LocVT = MVT::i64;
432 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
462 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
892 VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
921 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
1075 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1209 return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp117 if (LocVT == MVT::i64 && Offset < 6*8)
165 LocVT = MVT::i64;
337 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
343 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
344 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
451 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
510 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
615 // All integer register arguments are promoted by the caller to i64.
690 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1090 // Full register, just bitconvert into i64
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp441 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
467 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
490 case MVT::i64:
628 case MVT::i64:
821 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
851 case MVT::i64:
934 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
947 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
958 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1003 SrcVT != MVT::i32 && SrcVT != MVT::i64)
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