Searched refs:rN (Results 1 - 25 of 31) sorted by relevance

12

/external/compiler-rt/lib/builtins/arm/
H A D	sync_fetch_and_add_4.S	18 #define add_4(rD, rN, rM) add rD, rN, rM
H A D	sync_fetch_and_and_4.S	17 #define and_4(rD, rN, rM) and rD, rN, rM
H A D	sync_fetch_and_nand_4.S	17 #define nand_4(rD, rN, rM) bic rD, rN, rM
H A D	sync_fetch_and_or_4.S	17 #define or_4(rD, rN, rM) orr rD, rN, rM
H A D	sync_fetch_and_sub_4.S	18 #define sub_4(rD, rN, rM) sub rD, rN, rM
H A D	sync_fetch_and_xor_4.S	17 #define xor_4(rD, rN, rM) eor rD, rN, rM
H A D	sync_fetch_and_max_4.S	17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt)
H A D	sync_fetch_and_min_4.S	17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt)
H A D	sync_fetch_and_umax_4.S	17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi)
H A D	sync_fetch_and_umin_4.S	17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo)
H A D	sync-ops.h	51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ 52 cmp rN, rM ; \ 55 mov##cmp_kind rD, rN
/external/lzma/Asm/x86/
H A D	XzCrc64Opt.asm	11 rN equ r10 define 16 SRCDAT equ rN + rD 29 dec rN 36 mov rN, num_VAR 39 test rN, rN 47 cmp rN, 8 49 add rN, rD 50 mov num_VAR, rN 51 sub rN, 101 rN equ r7 define [all...]
H A D	7zCrcOpt.asm	9 rN equ r7 define 21 SRCDAT equ rN + rD + 4 * 42 dec rN 49 mov rN, num_VAR 51 test rN, rN 59 cmp rN, 16 61 add rN, rD 62 mov num_VAR, rN 63 sub rN, [all...]
H A D	AesOpt.asm	19 rN equ r0 define 31 mov rN, num 107 sub rN, ways 110 add rN, ways 124 sub rN, 1 161 sub rN, 1 215 sub rN, ways 218 add rN, ways 231 sub rN, 1
/external/valgrind/VEX/priv/
H A D	guest_arm_toIR.c	2369 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, argument 2372 vassert(rN < 16); 2376 DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12); 2379 getIRegA(rN), 2388 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM, argument 2392 vassert(rN < 16); 2403 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); 2413 rN, opChar, rM, imm5 == 0 ? 32 : imm5); 2425 rN, opChar, rM, imm5 == 0 ? 32 : imm5); 2436 DIS(buf, "[r%u, %cr%u, RRX]", rN, opCha 2458 mk_EA_reg_plusminus_imm8( UInt rN, UInt bU, UInt imm8, HChar* buf ) argument 2475 mk_EA_reg_plusminus_reg( UInt rN, UInt bU, UInt rM, HChar* buf ) argument 8334 UInt rN = INSN(19,16); local 10921 UInt rD = 99, rN = 99, rM = 99, rA = 99; local 12336 UInt rD = 99, rN = 99, rM = 99, rA = 99; local 12393 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99; local 12482 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99; local 12587 mk_ldm_stm( Bool arm, UInt rN, UInt bINC, UInt bBEFORE, UInt bW, UInt bL, UInt regList ) argument 12856 UInt rN = INSN(19,16); local 12993 UInt rN = INSN(19,16); local 13152 UInt rN = INSN(19,16); /* hi32 */ local 13172 UInt rN = INSN(19,16); /* hi32 */ local 13197 UInt rN = INSN(15,12); local 13218 UInt rN = INSN(15,12); local 13288 UInt rN = (INSN(7,7) << 4) | INSN(19,16); local 13429 UInt rN = INSN(19,16); local 13785 UInt rN = INSN(19,16); local 13934 UInt rN = INSN(19,16); local 14471 UInt rN = INSN(19,16); local 14482 UInt rN = INSN(19,16); local 14506 UInt rN = INSN(19,16); local 14776 UInt rN = (insn >> 16) & 0xF; /* 19:16 */ local 15108 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */ local 15336 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */ local 15517 UInt rN = (insn >> 16) & 0xF; local 15755 UInt rN = INSN(3,0); local 15777 UInt rN = INSN(3,0); local 15799 UInt rN = INSN(15,12); local 15953 UInt rN = INSN(3,0); local 16012 UInt rN = INSN(3,0); local 16062 UInt rN = INSN(19,16); local 16119 UInt rN = INSN(19,16); local 16173 UInt rN = INSN(19,16); local 16335 UInt rN = INSN(3,0); local 16379 UInt rN = INSN(3,0); local 16461 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */ local 16621 UInt rN = INSN(19,16); local 16651 UInt rN = INSN(19,16); local 16747 UInt rN = INSN(3,0); local 16769 UInt rN = INSN(3,0); local 16791 UInt rN = INSN(19,16); local 16817 UInt rN = INSN(19,16); local 16846 UInt rN = INSN(19,16); local 16872 UInt rN = INSN(19,16); local 16902 UInt rN = INSN(19,16); local 16931 UInt rN = INSN(19,16); local 16958 UInt rN = INSN(19,16); local 16987 UInt rN = INSN(19,16); local 17014 UInt rN = INSN(19,16); local 17043 UInt rN = INSN(19,16); local 17069 UInt rN = INSN(19,16); local 17094 UInt rN = INSN(19,16); local 17121 UInt rN = INSN(19,16); local 17148 UInt rN = INSN(19,16); local 17172 UInt rN = INSN(19,16); local 17196 UInt rN = INSN(19,16); local 17933 UInt rN = INSN0(2,0); local 17948 UInt rN = INSN0(2,0); local 18394 UInt rN = (h1 << 3) | INSN0(2,0); local 18470 UInt rN = INSN0(2,0); local 18651 UInt rN = INSN0(5,3); local 18672 UInt rN = INSN0(5,3); local 18694 UInt rN = INSN0(5,3); local 18719 UInt rN = INSN0(5,3); local 18742 UInt rN = INSN0(5,3); local 18760 UInt rN = INSN0(5,3); local 18780 UInt rN = INSN0(5,3); local 18814 UInt rN = INSN0(10,8); local 18854 UInt rN = INSN0(10,8); local 18909 UInt rN = INSN0(5,3); local 18934 UInt rN = INSN0(5,3); local 18959 UInt rN = INSN0(5,3); local 19005 UInt rN = INSN0(10,8); local 19051 UInt rN = INSN0(10,8); local 19314 UInt rN = INSN0(3,0); local 19384 UInt rN = INSN0(3,0); local 19411 UInt rN = INSN0(3,0); local 19438 UInt rN = INSN0(3,0); local 19460 UInt rN = INSN0(3,0); local 19492 UInt rN = INSN0(3,0); local 19526 UInt rN = INSN0(3,0); local 19555 UInt rN = INSN0(3,0); local 19611 UInt rN = INSN0(3,0); local 19660 UInt rN = INSN0(3,0); local 19739 UInt rN = INSN0(3,0); local 19808 UInt rN = INSN0(3,0); local 19873 UInt rN = INSN0(3,0); local 19910 UInt rN = INSN1(3,0); local 19952 UInt rN = INSN0(3,0); local 19993 UInt rN = INSN0(3,0); local 20121 UInt rN = INSN0(3,0); local 20313 UInt rN = INSN0(3,0); local 20462 UInt rN = INSN0(3,0); local 20591 UInt rN = INSN0(3,0); local 20766 UInt rN = INSN0(3,0); local 20814 UInt rN = INSN0(3,0); local 20928 UInt rN = INSN0(3,0); local 20943 UInt rN = INSN0(3,0); local 20962 UInt rN = INSN0(3,0); local 20982 UInt rN = INSN0(3,0); local 21003 UInt rN = INSN0(3,0); local 21044 UInt rN = INSN0(3,0); local 21076 UInt rN = INSN0(3,0); local 21116 UInt rN = INSN0(3,0); local 21138 UInt rN = INSN0(3,0); local 21175 UInt rN = INSN0(3,0); local 21221 UInt rN = INSN0(3,0); local 21250 UInt rN = INSN0(3,0); local 21368 UInt rN = INSN0(3,0); local 21395 UInt rN = INSN0(3,0); local 21417 UInt rN = INSN0(3,0); local 21437 UInt rN = INSN0(3,0); local 21459 UInt rN = INSN0(3,0); local 21489 UInt rN = INSN0(3,0); local 21517 UInt rN = INSN0(3,0); local 21588 UInt rN = INSN0(3,0); local 21598 UInt rN = INSN0(3,0); local 21608 UInt rN = INSN0(3,0); local 21675 UInt rN = INSN0(3,0); local 21698 UInt rN = INSN0(3,0); local 21719 UInt rN = INSN0(3,0); local 21740 UInt rN = INSN0(3,0); local 21769 UInt rN = INSN0(3,0); local 21799 UInt rN = INSN0(3,0); local 21820 UInt rN = INSN0(3,0); local 21844 UInt rN = INSN0(3,0); local 21868 UInt rN = INSN0(3,0); local 21882 UInt rN = INSN0(3,0); local [all...]
H A D	host_arm64_defs.c	1013 ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { argument 1018 i->ARM64in.VLdStH.rN = rN; 1023 ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { argument 1028 i->ARM64in.VLdStS.rN = rN; 1033 ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, UInt uimm12 ) { argument 1038 i->ARM64in.VLdStD.rN = rN; 1043 ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ) { 3266 UInt rN = iregEnc(i->ARM64in.Arith.argL); local 3292 UInt rN = iregEnc(i->ARM64in.Cmp.argL); local 3319 UInt rN = iregEnc(i->ARM64in.Logic.argL); local 3359 UInt rN = iregEnc(i->ARM64in.Test.argL); local 3378 UInt rN = iregEnc(i->ARM64in.Shift.argL); local 3811 UInt rN = iregEnc(i->ARM64in.VLdStH.rN); local 3828 UInt rN = iregEnc(i->ARM64in.VLdStS.rN); local 3845 UInt rN = iregEnc(i->ARM64in.VLdStD.rN); local 3862 UInt rN = iregEnc(i->ARM64in.VLdStQ.rN); local 3883 UInt rN = iregEnc(i->ARM64in.VCvtI2F.rS); local 3930 UInt rN = dregEnc(i->ARM64in.VCvtF2I.rS); local 5316 HReg rN = i->ARM64in.VMov.src; local [all...]
H A D	host_arm64_defs.h	681 HReg rN; member in struct:__anon19186::__anon19187::__anon19211 688 HReg rN; member in struct:__anon19186::__anon19187::__anon19212 695 HReg rN; member in struct:__anon19186::__anon19187::__anon19213 702 HReg rN; // address member in struct:__anon19186::__anon19187::__anon19214 912 extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, 914 extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, 916 extern ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, 918 extern ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN );
H A D	host_arm_defs.c	365 ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { argument 368 am->ARMamN.RR.rN = rN; 373 ARMAModeN *mkARMAModeN_R ( HReg rN ) { 376 am->ARMamN.R.rN = rN; 382 addHRegUse(u, HRmRead, am->ARMamN.R.rN); 384 addHRegUse(u, HRmRead, am->ARMamN.RR.rN); 391 am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN); 1504 ARMInstr_Add32( HReg rD, HReg rN, UInt imm32 ) argument 2839 UInt rN = 0; local 2973 UInt rN = iregEnc(i->ARMin.Alu.argL); local 3117 HReg rN = am->ARMam2.RI.reg; local 3164 HReg rN = am->ARMam2.RI.reg; local 3505 UInt rN = iregEnc(i->ARMin.VLdStD.amode->reg); local 3521 UInt rN = iregEnc(i->ARMin.VLdStS.amode->reg); local [all...]
H A D	host_arm_defs.h	215 HReg rN; member in struct:__anon19260::__anon19261::__anon19262 219 HReg rN; member in struct:__anon19260::__anon19261::__anon19263 942 /* Note: rD != rN */ 944 HReg rN; member in struct:__anon19289::__anon19290::__anon19336 1017 extern ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 );
H A D	host_arm64_isel.c	2189 HReg rN = iselIntExpr_R(env, e->Iex.Load.addr); local 2191 addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, rN)); 3036 HReg rN = get_baseblock_register(); local 3037 addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, rD, rN, offs)); 3223 HReg rN = get_baseblock_register(); local 3224 addInstr(env, ARM64Instr_VLdStS(True/*isLoad*/, rD, rN, offs)); 3370 HReg rN = get_baseblock_register(); local 3371 addInstr(env, ARM64Instr_VLdStH(True/*isLoad*/, rD, rN, offs));
H A D	guest_arm64_toIR.c	2814 UInt rN = INSN(9,5); local 2823 assign(argL, getIRegOrZR(is64, rN)); 2834 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), 2856 UInt rN = INSN(9,5); local 2869 assign(argL, getIRegOrZR(is64, rN)); 2897 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), 2922 UInt rN = INSN(9,5); local 2930 assign(argL, getIRegOrZR(is64, rN)); 2951 if (rN == 31/*zr*/ && sh == 0/*LSL*/ && imm6 == 0 && bN == 0) { 2956 nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), 4816 UInt rN = INSN(9,5); local [all...]
/external/valgrind/none/tests/arm/
H A D	vfp.stdout.exp	905 vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 906 vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 907 vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 908 vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x00000aa0 0x00000bb1 0x00000cc2 0x00000dd3 909 vldmia rN!, qD1; vldmia rN!, qD [all...]
H A D	vfp.c	578 printf("vldmia rN!, qD1; vldmia rN!, qD2 :: Result 0x%08x 0x%08x 0x%08x 0x%08x\n", \ 601 printf("vldmdb rN!, qD1; vldmia rN!, qD2 :: Result 0x%08x 0x%08x 0x%08x 0x%08x\n", \ 605 #define TESTINSN_VLDR(instruction, dD, rN, rNval, offset) \ 611 "mov " #rN ", %1\n\t" \ 618 printf("%s :: dD 0x%08x 0x%08x rN 0x%08x\n", \
/external/libvpx/libvpx/third_party/libyuv/source/
H A D	x86inc.asm	127 ; rN and rNq are the native-size register holding function argument N
/external/libvpx/libvpx/third_party/x86inc/
H A D	x86inc.asm	226 ; rN and rNq are the native-size register holding function argument N

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Indexes created Thu Dec 22 05:45:36 CET 2016