Searched refs:v10 (Results 1 - 25 of 117) sorted by relevance

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/external/icu/icu4j/eclipse-build/features.template/com.ibm.icu/
H A Dbuild.properties6 # http://www.eclipse.org/legal/epl-v10.html
12 epl-v10.html,\
/external/icu/icu4j/eclipse-build/features.template/com.ibm.icu.base/
H A Dbuild.properties6 # http://www.eclipse.org/legal/epl-v10.html
12 epl-v10.html,\
/external/v8/test/mjsunit/compiler/
H A Dregress-gap.js39 function select(n, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10) {
50 v9 = v10;
51 v10 = tmp;
56 function select_while(n, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10) {
68 v9 = v10;
69 v10 = tmp;
/external/libavc/common/armv8/
H A Dih264_deblk_chroma_av8.s101 uaddl v10.8h, v7.8b, v1.8b //Q4,Q5 = q0 + p1
110 umlal v10.8h, v3.8b, v31.8b //Q5,Q4 = (X2(q1U) + q0U + p1U)
124 rshrn v9.8b, v10.8h, #2 //Q4 = (X2(q1U) + q0U + p1U + 2) >> 2
127 rshrn v10.8b, v14.8h, #2 //
129 mov v10.d[1], v11.d[0]
131 bit v10.16b, v4.16b , v18.16b //
133 mov v11.d[0], v10.d[1]
135 st2 {v10.8b, v11.8b}, [x4], x1 //
206 mov v10.16b, v2.16b
209 mov v4.16b, v10
[all...]
H A Dih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s151 ld1 {v10.2s, v11.2s}, [x7], x2 // Vector load from src[5_0]
153 uaddl v24.8h, v0.8b, v10.8b
195 umlsl v16.8h, v10.8b, v31.8b
242 umlal v16.8h, v10.8b, v30.8b
288 umlal v0.8h, v10.8b, v30.8b
338 mov v2.16b, v10.16b
355 ld1 {v10.2s, v11.2s}, [x7], x2 // Vector load from src[9_0]
357 uaddl v24.8h, v0.8b, v10.8b
397 umlsl v16.8h, v10.8b, v31.8b
442 umlal v16.8h, v10
[all...]
H A Dih264_weighted_bi_pred_av8.s172 ld1 {v10.s}[0], [x1], x4 //load row 3 in source 2
173 ld1 {v10.s}[1], [x1], x4 //load row 4 in source 2
175 uxtl v10.8h, v10.8b //converting rows 3,4 in source 2 to 16-bit
179 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for rows 3,4
199 ld1 {v10.8b}, [x1], x4 //load row 2 in source 2
207 uxtl v10.8h, v10.8b //converting row 2 in source 2 to 16-bit
213 mla v8.8h, v10.8h , v2.h[2] //weight 2 mult. for row 2
245 ld1 {v10
[all...]
H A Dih264_weighted_pred_av8.s174 ld1 {v10.8b}, [x0], x2 //load row 4 in source
179 uxtl v10.8h, v10.8b //converting row 4 to 16-bit
182 mul v10.8h, v10.8h , v2.h[0] //weight mult. for row 4
188 srshl v10.8h, v10.8h , v0.8h //rounds off the weighted samples from row 4
193 saddw v10.8h, v10.8h , v3.8b //adding offset for row 4
196 sqxtun v10
[all...]
H A Dih264_deblk_luma_av8.s99 ld1 {v10.8b, v11.8b}, [x0], x1 //p2 values are loaded into q5
107 mov v10.d[1], v11.d[0]
124 uabd v28.16b, v10.16b, v6.16b
156 uaddl v10.8h, v16.8b, v10.8b //Q14,Q5 = p2 + (p0+q0+1)>>1
164 sub v10.8h, v10.8h , v16.8h //
168 sqshrn v28.8b, v10.8h, #1 //Q14 = i_macro_p1
256 ld1 {v10.8b, v11.8b}, [x14] //load p1 to Q5
260 mov v10
[all...]
H A Dih264_inter_pred_filters_luma_vert_av8.s132 ld1 {v10.2s, v11.2s}, [x0], x2 // Vector load from src[5_0]
136 uaddl v14.8h, v0.8b, v10.8b // temp = src[0_0] + src[5_0]
147 uaddl v18.8h, v4.8b, v10.8b
159 uaddl v12.8h, v8.8b, v10.8b
174 uaddl v12.8h, v10.8b, v0.8b
191 uaddl v16.8h, v10.8b, v4.8b // temp2 = src[1_0] + src[4_0]
213 uaddl v14.8h, v8.8b, v10.8b
216 ld1 {v10.2s, v11.2s}, [x0], x2
230 uaddl v14.8h, v10.8b, v0.8b
242 uaddl v16.8h, v10
[all...]
H A Dih264_inter_pred_luma_horz_hpel_vert_qpel_av8.s175 uaddl v10.8h, v2.8b, v3.8b
180 mla v8.8h, v10.8h , v22.8h
182 uaddl v10.8h, v1.8b, v4.8b
184 mls v8.8h, v10.8h , v24.8h
186 uaddl v10.8h, v0.8b, v5.8b
194 mla v10.8h, v12.8h , v22.8h
198 mls v10.8h, v12.8h , v24.8h
205 st1 {v10.4s}, [x9], x6 // store temp buffer 2
243 add v30.8h, v10.8h , v12.8h
271 add v28.8h, v10
[all...]
H A Dih264_inter_pred_luma_vert_qpel_av8.s139 ld1 {v10.2s, v11.2s}, [x0], x2 // Vector load from src[5_0]
143 uaddl v14.8h, v0.8b, v10.8b // temp = src[0_0] + src[5_0]
154 uaddl v18.8h, v4.8b, v10.8b
169 uaddl v12.8h, v8.8b, v10.8b
183 uaddl v12.8h, v10.8b, v0.8b
205 uaddl v16.8h, v10.8b, v4.8b // temp2 = src[1_0] + src[4_0]
230 uaddl v14.8h, v8.8b, v10.8b
233 ld1 {v10.2s, v11.2s}, [x0], x2
252 uaddl v14.8h, v10.8b, v0.8b
264 uaddl v16.8h, v10
[all...]
H A Dih264_iquant_itrans_recon_av8.s179 add v10.4h, v4.4h , v7.4h // x0+x3
189 trn1 v4.4h, v10.4h, v11.4h
190 trn2 v5.4h, v10.4h, v11.4h
194 trn1 v10.2s, v4.2s, v6.2s // 0
203 add v14.4h, v10.4h, v12.4h // x0 = q0 + q2//
204 sub v15.4h, v10.4h, v12.4h // x1 = q0 - q2//
366 add v10.4h, v4.4h , v7.4h // x0+x3
378 trn1 v4.4h, v10.4h, v11.4h
379 trn2 v5.4h, v10.4h, v11.4h
383 trn1 v10
[all...]
/external/libjpeg-turbo/simd/
H A Djsimd_arm64_neon.S262 st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
305 st1 {v8.4h, v9.4h, v10.4h, v11.4h}, [sp], 32 /* save NEON registers */
330 mov v10.16b, v14.16b
339 smlal v10.4s, ROW5L.4h, XFIX_2_053119869_MINUS_2_562915447
341 smlsl v10.4s, ROW3L.4h, XFIX_2_562915447
351 add v2.4s, v6.4s, v10.4s
353 sub v6.4s, v6.4s, v10.4s
354 saddl v10.4s, ROW0L.4h, ROW4L.4h
360 shl v10.4s, v10
[all...]
/external/llvm/test/MC/AArch64/
H A Dneon-max-min.s85 fmin v10.4h, v15.4h, v22.4h
86 fmin v10.8h, v15.8h, v22.8h
87 fmin v10.2s, v15.2s, v22.2s
91 // CHECK: fmin v10.4h, v15.4h, v22.4h // encoding: [0xea,0x35,0xd6,0x0e]
92 // CHECK: fmin v10.8h, v15.8h, v22.8h // encoding: [0xea,0x35,0xd6,0x4e]
93 // CHECK: fmin v10.2s, v15.2s, v22.2s // encoding: [0xea,0xf5,0xb6,0x0e]
115 fminnm v10.4h, v15.4h, v22.4h
116 fminnm v10.8h, v15.8h, v22.8h
117 fminnm v10.2s, v15.2s, v22.2s
121 // CHECK: fminnm v10
[all...]
H A Dneon-max-min-pairwise.s85 fminp v10.4h, v15.4h, v22.4h
87 fminp v10.2s, v15.2s, v22.2s
91 // CHECK: fminp v10.4h, v15.4h, v22.4h // encoding: [0xea,0x35,0xd6,0x2e]
93 // CHECK: fminp v10.2s, v15.2s, v22.2s // encoding: [0xea,0xf5,0xb6,0x2e]
115 fminnmp v10.4h, v15.4h, v22.4h
117 fminnmp v10.2s, v15.2s, v22.2s
121 // CHECK: fminnmp v10.4h, v15.4h, v22.4h // encoding: [0xea,0x05,0xd6,0x2e]
123 // CHECK: fminnmp v10.2s, v15.2s, v22.2s // encoding: [0xea,0xc5,0xb6,0x2e]
H A Dneon-scalar-by-elem-mul.s30 fmulx s13, s21, v10.s[3]
38 // CHECK: fmulx s13, s21, v10.s[3] // encoding: [0xad,0x9a,0xaa,0x7f]
/external/clang/test/CodeGen/
H A Dvector-alignment.c52 double __attribute__((vector_size(40))) v10; variable
53 // SSE: @v10 {{.*}}, align 16
54 // AVX: @v10 {{.*}}, align 32
55 // AVX512: @v10 {{.*}}, align 64
/external/libhevc/common/arm64/
H A Dihevc_sao_band_offset_chroma.s163 LD1 {v10.8b},[x14],#8 //band_table_v.val[1]
223 ADD v14.8b, v10.8b , v30.8b //band_table_v.val[1] = vadd_u8(band_table_v.val[1], band_pos_v)
235 ADD v10.8b, v14.8b , v28.8b //band_table_v.val[1] = vadd_u8(band_table_v.val[1], vdup_n_u8(pi1_sao_offset_v[2]))
266 cmhs v19.8b, v29.8b , v10.8b //vcle_u8(band_table.val[1], vdup_n_u8(16))
268 ORR v10.8b, v10.8b , v19.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
280 AND v10.8b, v10.8b , v19.8b //band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
296 mov v9.d[1],v10.d[0]
297 mov v10
[all...]
H A Dihevc_inter_pred_chroma_horz.s197 ld1 { v10.2s},[x4],x11 //vector load pu1_src
240 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
295 ld1 { v10.2s},[x4],x11 //vector load pu1_src
354 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
394 ld1 { v10.2s},[x4],x11 //vector load pu1_src
425 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
499 umull v10.8h, v5.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
500 umlsl v10.8h, v4.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)//
504 umlal v10.8h, v6.8b, v26.8b //mul_res = vmlsl_u8(src[0_0], coeffabs_0)//
505 umlsl v10
[all...]
H A Dihevc_itrans_recon_32x32.s211 ld1 {v10.4h},[x0],x6
230 smull v20.4s, v10.4h, v0.h[0]
234 smull v22.4s, v10.4h, v0.h[0]
237 smull v16.4s, v10.4h, v0.h[0]
240 smull v18.4s, v10.4h, v0.h[0]
280 ld1 {v10.4h},[x0],x6
300 smlal v20.4s, v10.4h, v2.h[0]
304 smlal v22.4s, v10.4h, v6.h[0]
307 smlsl v16.4s, v10.4h, v6.h[0]
310 smlsl v18.4s, v10
[all...]
H A Dihevc_intra_pred_chroma_mode_27_to_33.s169 umull v10.8h, v23.8b, v30.8b //(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
172 umlal v10.8h, v9.8b, v31.8b //(i row)vmull_u8(ref_main_idx_1, dup_const_fract)
187 rshrn v10.8b, v10.8h,#5 //(i row)shift_res = vrshrn_n_u16(add_res, 5)
201 st1 {v10.8b},[x2],#8 //(i row)
230 umull v10.8h, v23.8b, v30.8b //(v)vmull_u8(ref_main_idx, dup_const_32_fract)
233 umlal v10.8h, v9.8b, v31.8b //(v)vmull_u8(ref_main_idx_1, dup_const_fract)
253 rshrn v10.8b, v10.8h,#5 //(v)shift_res = vrshrn_n_u16(add_res, 5)
267 st1 {v10
[all...]
H A Dihevc_intra_pred_filters_luma_mode_19_to_25.s284 umull v10.8h, v23.8b, v30.8b //(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
287 umlal v10.8h, v9.8b, v31.8b //(i row)vmull_u8(ref_main_idx_1, dup_const_fract)
301 rshrn v10.8b, v10.8h,#5 //(i row)shift_res = vrshrn_n_u16(add_res, 5)
315 st1 {v10.8b},[x2],#8 //(i row)
342 umull v10.8h, v23.8b, v30.8b //(v)vmull_u8(ref_main_idx, dup_const_32_fract)
345 umlal v10.8h, v9.8b, v31.8b //(v)vmull_u8(ref_main_idx_1, dup_const_fract)
364 rshrn v10.8b, v10.8h,#5 //(v)shift_res = vrshrn_n_u16(add_res, 5)
378 st1 {v10
[all...]
H A Dihevc_intra_pred_luma_mode_27_to_33.s174 umull v10.8h, v23.8b, v30.8b //(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
177 umlal v10.8h, v9.8b, v31.8b //(i row)vmull_u8(ref_main_idx_1, dup_const_fract)
192 rshrn v10.8b, v10.8h,#5 //(i row)shift_res = vrshrn_n_u16(add_res, 5)
206 st1 {v10.8b},[x2],#8 //(i row)
235 umull v10.8h, v23.8b, v30.8b //(v)vmull_u8(ref_main_idx, dup_const_32_fract)
238 umlal v10.8h, v9.8b, v31.8b //(v)vmull_u8(ref_main_idx_1, dup_const_fract)
258 rshrn v10.8b, v10.8h,#5 //(v)shift_res = vrshrn_n_u16(add_res, 5)
272 st1 {v10
[all...]
H A Dihevc_inter_pred_chroma_horz_w16out.s212 ld1 { v10.2s},[x4],x11 //vector load pu1_src
252 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
302 ld1 { v10.2s},[x4],x11 //vector load pu1_src
347 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
391 ld1 { v10.2s},[x4],x11 //vector load pu1_src
415 umull v22.8h, v10.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
482 umull v10.8h, v5.8b, v25.8b //mul_res = vmull_u8(src[0_3], coeffabs_3)//
483 umlsl v10.8h, v4.8b, v24.8b //mul_res = vmlsl_u8(src[0_2], coeffabs_2)//
486 umlal v10.8h, v6.8b, v26.8b //mul_res = vmlsl_u8(src[0_0], coeffabs_0)//
487 umlsl v10
[all...]
/external/libavc/encoder/armv8/
H A Dih264e_evaluate_intra16x16_modes_av8.s131 dup v10.8h, w10
139 add v0.4h, v0.4h, v10.4h
160 ld1 {v10.8b}, [x6], #8
172 uabdl v16.8h, v0.8b, v10.8b
192 uabal v16.8h, v2.8b, v10.8b
208 uabal v16.8h, v4.8b, v10.8b
224 uabal v16.8h, v6.8b, v10.8b
241 uabal v16.8h, v0.8b, v10.8b
257 uabal v16.8h, v2.8b, v10.8b
273 uabal v16.8h, v4.8b, v10
[all...]

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