/external/clang/test/CodeGen/ |
H A D | mips-vector-arg.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef 24 extern test_v4i32_2(v4i32, int, v4i32); 25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
|
H A D | mips-inline-asm-modifiers.c | 8 typedef int v4i32 __attribute__((vector_size(16))); typedef 17 v4i32 v4i32_r;
|
H A D | mips-vector-return.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef 28 v4i32 test_v4i32(int a) { 29 return (v4i32){0, a, 0, 0};
|
H A D | compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); typedef 7 v4i32 *y = &(v4i32){1,2,3,4};
|
H A D | mips-varargs.c | 10 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef 130 v4i32 v = va_arg(va, v4i32);
|
H A D | systemz-abi-vector.c | 29 typedef __attribute__((vector_size(16))) int v4i32; typedef 90 v4i32 pass_v4i32(v4i32 arg) { return arg; }
|
H A D | x86_32-arguments-darwin.c | 224 typedef int v4i32 __attribute__((__vector_size__(16))); typedef 228 v4i32 f55(v4i32 arg) { return arg+arg; }
|
/external/llvm/lib/Target/AMDGPU/ |
H A D | SITypeRewriter.cpp | 39 Type *v4i32; member in class:__anon12510::SITypeRewriter 60 v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4); 81 PointerType::get(v4i32,PtrTy->getPointerAddressSpace())); 105 Args.push_back(Builder.CreateBitCast(Arg, v4i32)); 106 Types.push_back(v4i32); 108 Name = Name + ".v4i32"; 141 if (I.getDestTy() != v4i32) { 146 if (Op->getSrcTy() == v4i32) {
|
/external/libvpx/libvpx/vp8/encoder/mips/msa/ |
H A D | dct_msa.c | 48 v4i32 tmp0_m; \ 49 v4i32 one_m = __msa_ldi_w(1); \ 60 v4i32 tmp0_m; \ 62 v4i32 one_m = __msa_ldi_w(1); \ 75 v4i32 out0, out1, out2, out3; 88 out0 = (v4i32)__msa_ilvev_h(zero, in1); 90 out1 = __msa_splati_w((v4i32)coeff, 0); 107 out1 = __msa_splati_w((v4i32)coeff, 1); 111 out1 += (v4i32)temp1; 123 v4i32 vec0_ [all...] |
H A D | encodeopt_msa.c | 20 v4i32 diff0, diff1; 52 v4i32 diff0, diff1; 59 mask0 = (v16u8)__msa_insve_w((v4i32)mask0, 0, (v4i32)zero); 86 diff0 = (v4i32)__msa_bmnz_v(zero, (v16u8)diff0, mask0); 98 diff0 = (v4i32)__msa_bmnz_v(zero, (v16u8)diff0, mask0); 121 v4i32 diff0, diff1;
|
H A D | temporal_filter_msa.c | 27 v4i32 const3, const16, filter_wt, strength; 28 v4i32 mod0_w, mod1_w, mod2_w, mod3_w; 29 v4i32 diff0_r, diff0_l, diff1_r, diff1_l; 30 v4i32 frame2_0, frame2_1, frame2_2, frame2_3; 31 v4i32 acc0, acc1, acc2, acc3; 144 v4i32 const3, const16; 145 v4i32 filter_wt, strength; 146 v4i32 mod0_w, mod1_w, mod2_w, mod3_w; 147 v4i32 diff0_r, diff0_l, diff1_r, diff1_l; 148 v4i32 frame2_ [all...] |
/external/libvpx/libvpx/vp9/encoder/mips/msa/ |
H A D | vp9_avg_msa.c | 30 sum = (v4u32)__msa_srari_w((v4i32)sum, 6); 31 sum_out = __msa_copy_u_w((v4i32)sum, 0); 52 sum1 = (v4u32)__msa_srari_w((v4i32)sum2, 4); 53 sum_out = __msa_copy_u_w((v4i32)sum1, 0);
|
H A D | vp9_temporal_filter_msa.c | 28 v4i32 cnst3, cnst16, filt_wt, strength; 29 v4i32 mod0_w, mod1_w, mod2_w, mod3_w; 30 v4i32 diff0_r, diff0_l, diff1_r, diff1_l; 31 v4i32 frm2_rr, frm2_rl, frm2_lr, frm2_ll; 32 v4i32 acc0, acc1, acc2, acc3; 157 v4i32 cnst3, cnst16, filt_wt, strength; 158 v4i32 mod0_w, mod1_w, mod2_w, mod3_w; 159 v4i32 diff0_r, diff0_l, diff1_r, diff1_l; 160 v4i32 frm2_rr, frm2_rl, frm2_lr, frm2_ll; 161 v4i32 acc [all...] |
/external/libvpx/libvpx/vp8/common/mips/msa/ |
H A D | vp8_macros_msa.h | 29 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__) 40 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__) 452 out0_m = __msa_copy_u_w((v4i32)in0, idx0); \ 453 out1_m = __msa_copy_u_w((v4i32)in0, idx1); \ 454 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \ 455 out3_m = __msa_copy_u_w((v4i32)in1, idx3); \ 673 #define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__) 687 out0 = (RTYPE)__msa_dotp_s_d((v4i32)mult0, (v4i32)cnst0); \ 688 out1 = (RTYPE)__msa_dotp_s_d((v4i32)mult [all...] |
H A D | idct_msa.c | 32 v4i32 tmp1_m, tmp2_m; \ 33 v4i32 sinpi8_sqrt2_m = __msa_fill_w(sinpi8sqrt2); \ 69 v4i32 a1_m, b1_m, c1_m, d1_m; \ 70 v4i32 c_tmp1_m, c_tmp2_m, d_tmp1_m, d_tmp2_m; \ 71 v4i32 const_cospi8sqrt2minus1_m, sinpi8_sqrt2_m; \ 91 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; 92 v4i32 res0, res1, res2, res3; 148 v4i32 in0, in1, in2, in3, a1, b1, c1, d1; 149 v4i32 hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; 186 v4i32 hz0_ [all...] |
H A D | postproc_msa.c | 559 v4i32 flimit_vec; 588 v4i32 sum_sq0, sum_sq1, sum_sq2, sum_sq3; 589 v4i32 sub0, sub1, sub2, sub3; 590 v4i32 sum0_w, sum1_w, sum2_w, sum3_w; 591 v4i32 mul0, mul1, mul2, mul3; 592 v4i32 total0, total1, total2, total3; 689 v4i32 flimit_vec; 694 v4i32 sub0, sub1, sub2, sub3, total0, total1, total2, total3; 707 v4i32 mul0 = { 0 }; 708 v4i32 mul [all...] |
/external/libvpx/libvpx/vpx_dsp/mips/ |
H A D | macros_msa.h | 28 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__) 38 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__) 489 out0_m = __msa_copy_u_w((v4i32)in, 0); \ 490 out1_m = __msa_copy_u_w((v4i32)in, 1); \ 511 out0_m = __msa_copy_u_w((v4i32)in0, idx0); \ 512 out1_m = __msa_copy_u_w((v4i32)in0, idx1); \ 513 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \ 514 out3_m = __msa_copy_u_w((v4i32)in1, idx3); \ 612 #define SLDI_B2_0_SW(...) SLDI_B2_0(v4i32, __VA_ARGS__) 727 #define DOTP_SH2_SW(...) DOTP_SH2(v4i32, __VA_ARGS_ [all...] |
H A D | txfm_macros_msa.h | 18 v4i32 s0_m, s1_m, s2_m, s3_m; \ 20 s0_m = (v4i32)__msa_fill_h(cnst1); \ 36 v4i32 tp0_m, tp1_m, tp2_m, tp3_m, tp4_m; \ 37 v4i32 tp5_m, tp6_m, tp7_m, tp8_m, tp9_m; \ 53 v4i32 tp0_m, tp1_m; \ 63 v4i32 madd0_m, madd1_m, madd2_m, madd3_m; \ 76 v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m, m4_m, m5_m; \
|
H A D | intrapred_msa.c | 167 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 3); 169 val0 = __msa_copy_u_w((v4i32)store, 0); 182 data = (v16i8)__msa_insert_w((v4i32)data, 0, val0); 185 sum_w = (v4u32)__msa_srari_w((v4i32)sum_w, 2); 187 val0 = __msa_copy_u_w((v4i32)store, 0); 196 out = __msa_copy_u_w((v4i32)store, 0); 217 sum_w = (v4u32)__msa_pckev_w((v4i32)sum_d, (v4i32)sum_d); 219 sum_w = (v4u32)__msa_srari_w((v4i32)sum_d, 4); 242 sum_w = (v4u32)__msa_srari_w((v4i32)sum_ [all...] |
H A D | fwd_txfm_msa.h | 19 v4i32 vec_w_m; \ 35 v4i32 vec4_m, vec5_m, vec6_m, vec7_m; \ 308 v4i32 temp_m; \ 309 v4i32 one_m = __msa_ldi_w(1); \ 339 v4i32 s0_m, s1_m, s2_m, s3_m, s4_m, s5_m, s6_m, s7_m; \ 341 v4i32 k0_m = __msa_fill_w((int32_t) const0); \ 357 out0 = __msa_pckev_w((v4i32)tp0_m, (v4i32)tp1_m); \ 358 out1 = __msa_pckev_w((v4i32)tp2_m, (v4i32)tp3_ [all...] |
H A D | variance_msa.c | 49 v4i32 vec, var = { 0 }; 75 v4i32 vec, var = { 0 }; 101 v4i32 vec, var = { 0 }; 141 v4i32 vec, var = { 0 }; 186 v4i32 vec, var = { 0 }; 233 v4i32 vec, var = { 0 }; 272 v4i32 vec, var = { 0 }; 306 v4i32 src0_l, src1_l, src2_l, src3_l; 307 v4i32 src0_r, src1_r, src2_r, src3_r; 343 v4i32 va [all...] |
H A D | vpx_convolve_avg_msa.c | 30 out0 = __msa_copy_u_w((v4i32)dst0, 0); 31 out1 = __msa_copy_u_w((v4i32)dst1, 0); 32 out2 = __msa_copy_u_w((v4i32)dst2, 0); 33 out3 = __msa_copy_u_w((v4i32)dst3, 0); 46 out0 = __msa_copy_u_w((v4i32)dst0, 0); 47 out1 = __msa_copy_u_w((v4i32)dst1, 0);
|
/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 151 { ISD::SHL, MVT::v4i32, 1 }, 152 { ISD::SRL, MVT::v4i32, 1 }, 153 { ISD::SRA, MVT::v4i32, 1 }, 184 { ISD::SHL, MVT::v4i32, 1 }, 185 { ISD::SRL, MVT::v4i32, 2 }, 186 { ISD::SRA, MVT::v4i32, 2 }, 250 { ISD::SHL, MVT::v4i32, 1 }, // pslld 259 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 268 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 275 { ISD::SDIV, MVT::v4i32, 1 [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 79 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 80 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 83 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 84 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 103 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 104 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 127 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 128 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 347 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 370 {ISD::VECTOR_SHUFFLE, MVT::v4i32, [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 219 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
|