11452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee /* 21452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * Generic 32-bit floating-point operation. Provide an "instr" line that 31452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * specifies an instruction that performs "s2 = s0 op s1". Because we 41452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * use the "softfp" ABI, this must be an instruction, not a function call. 51452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * 61452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * For: add-float, sub-float, mul-float, div-float 71452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee */ 81452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee /* floatop vAA, vBB, vCC */ 91452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee FETCH r0, 1 @ r0<- CCBB 101452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee mov r9, rINST, lsr #8 @ r9<- AA 111452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee mov r3, r0, lsr #8 @ r3<- CC 121452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee and r2, r0, #255 @ r2<- BB 131452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 141452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 151452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee flds s1, [r3] @ s1<- vCC 161452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee flds s0, [r2] @ s0<- vBB 171452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee 181452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 191452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee $instr @ s2<- op 201452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee GET_INST_OPCODE ip @ extract opcode from rINST 211452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 221452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee fsts s2, [r9] @ vAA<- s2 231452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee GOTO_OPCODE ip @ jump to next instruction 24