1200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 2200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This file was generated automatically by gen-mterp.py for 'mips'. 3200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * --> DO NOT EDIT <-- 5200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/header.S */ 8200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Copyright (C) 2016 The Android Open Source Project 10200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 11200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Licensed under the Apache License, Version 2.0 (the "License"); 12200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * you may not use this file except in compliance with the License. 13200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * You may obtain a copy of the License at 14200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 15200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * http://www.apache.org/licenses/LICENSE-2.0 16200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 17200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Unless required by applicable law or agreed to in writing, software 18200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * distributed under the License is distributed on an "AS IS" BASIS, 19200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * See the License for the specific language governing permissions and 21200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * limitations under the License. 22200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 23200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 24200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 25200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung Art assembly interpreter notes: 26200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 27200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 28200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung handle invoke, allows higher-level code to create frame & shadow frame. 29200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 30200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung Once that's working, support direct entry code & eliminate shadow frame (and 31200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung excess locals allocation. 32200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 33200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the 34200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung base of the vreg array within the shadow frame. Access the other fields, 35200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 36200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung the shadow frame mechanism of double-storing object references - via rFP & 37200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung number_of_vregs_. 38200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 39200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 40200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 41200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#include "asm_support.h" 42200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 43200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if (__mips==32) && (__mips_isa_rev>=2) 44200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define MIPS32REVGE2 /* mips32r2 and greater */ 45200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if (__mips==32) && (__mips_isa_rev>=5) 46200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define FPU64 /* 64 bit FPU */ 47200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if (__mips==32) && (__mips_isa_rev>=6) 48200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define MIPS32REVGE6 /* mips32r6 and greater */ 49200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 50200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 51200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 52200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 53200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* MIPS definitions and declarations 54200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 55200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung reg nick purpose 56200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s0 rPC interpreted program counter, used for fetching instructions 57200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s1 rFP interpreted frame pointer, used for accessing locals and args 58200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s2 rSELF self (Thread) pointer 59200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s3 rIBASE interpreted instruction base pointer, used for computed goto 60200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s4 rINST first 16-bit code unit of current instruction 61200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s6 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 62200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung*/ 63200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 64200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* single-purpose registers, given names for clarity */ 65200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rPC s0 66200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rFP s1 67200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rSELF s2 68200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rIBASE s3 69200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rINST s4 70200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rOBJ s5 71200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rREFS s6 72200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rTEMP s7 73200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 74200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rARG0 a0 75200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rARG1 a1 76200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rARG2 a2 77200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rARG3 a3 78200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rRESULT0 v0 79200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define rRESULT1 v1 80200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 81200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* GP register definitions */ 82200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define zero $0 /* always zero */ 83200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define AT $at /* assembler temp */ 84200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define v0 $2 /* return value */ 85200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define v1 $3 86200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define a0 $4 /* argument registers */ 87200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define a1 $5 88200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define a2 $6 89200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define a3 $7 90200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t0 $8 /* temp registers (not saved across subroutine calls) */ 91200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t1 $9 92200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t2 $10 93200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t3 $11 94200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t4 $12 95200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t5 $13 96200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t6 $14 97200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t7 $15 98200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ta0 $12 /* alias */ 99200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ta1 $13 100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ta2 $14 101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ta3 $15 102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s0 $16 /* saved across subroutine calls (callee saved) */ 103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s1 $17 104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s2 $18 105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s3 $19 106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s4 $20 107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s5 $21 108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s6 $22 109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s7 $23 110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t8 $24 /* two more temp registers */ 111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define t9 $25 112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define k0 $26 /* kernel temporary */ 113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define k1 $27 114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define gp $28 /* global pointer */ 115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define sp $29 /* stack pointer */ 116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define s8 $30 /* one more callee saved */ 117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ra $31 /* return address */ 118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* FP register definitions */ 120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fv0 $f0 121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fv0f $f1 122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fv1 $f2 123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fv1f $f3 124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fa0 $f12 125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fa0f $f13 126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fa1 $f14 127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fa1f $f15 128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft0 $f4 129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft0f $f5 130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft1 $f6 131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft1f $f7 132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft2 $f8 133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft2f $f9 134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft3 $f10 135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft3f $f11 136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft4 $f16 137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft4f $f17 138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft5 $f18 139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ft5f $f19 140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs0 $f20 141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs0f $f21 142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs1 $f22 143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs1f $f23 144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs2 $f24 145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs2f $f25 146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs3 $f26 147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs3f $f27 148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs4 $f28 149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs4f $f29 150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs5 $f30 151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fs5f $f31 152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifndef MIPS32REVGE6 154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fcc0 $fcc0 155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define fcc1 $fcc1 156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * to access other shadow frame fields, we need to use a backwards offset. Define those here. 161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) 171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define MTERP_PROFILE_BRANCHES 1 173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define MTERP_LOGGING 0 174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * be done *before* something throws. 178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * It's okay to do this more than once. 180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * offset into the code_items_[] array. For effiency, we will "export" the 184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * to convert to a dex pc when needed. 186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define EXPORT_PC() \ 188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rPC, OFF_FP_DEX_PC_PTR(rFP) 189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define EXPORT_DEX_PC(tmp) \ 191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw tmp, OFF_FP_CODE_ITEM(rFP) \ 192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rPC, OFF_FP_DEX_PC_PTR(rFP) \ 193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu tmp, CODEITEM_INSNS_OFFSET \ 194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu tmp, rPC, tmp \ 195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra tmp, tmp, 1 \ 196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw tmp, OFF_FP_DEX_PC(rFP) 197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Fetch the next instruction from rPC into rINST. Does not advance rPC. 200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define FETCH_INST() lhu rINST, (rPC) 202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Fetch the next instruction from the specified offset. Advances rPC 205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * to point to the next instruction. "_count" is in 16-bit code units. 206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This must come AFTER anything that can throw an exception, or the 208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * exception catch may miss. (This also implies that it must come after 209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * EXPORT_PC().) 210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \ 212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rPC, rPC, ((_count) * 2) 213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The operation performed here is similar to FETCH_ADVANCE_INST, except the 216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * src and dest registers are parameterized (not hard-wired to rPC and rINST). 217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lhu _dreg, ((_count)*2)(_sreg) ; \ 220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu _sreg, _sreg, (_count)*2 221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rINST ahead of possible exception point. Be sure to manually advance rPC 225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * later. 226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define PREFETCH_INST(_count) lhu rINST, ((_count)*2)(rPC) 228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Advance rPC by some number of code units. */ 230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ADVANCE(_count) addu rPC, rPC, ((_count) * 2) 231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Fetch the next instruction from an offset specified by rd. Updates 234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rPC to point to the next instruction. "rd" must specify the distance 235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * in bytes, *not* 16-bit code units, and may be a signed value. 236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define FETCH_ADVANCE_INST_RB(rd) addu rPC, rPC, rd; \ 238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lhu rINST, (rPC) 239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Fetch a half-word code unit from an offset past the current PC. The 242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "_count" value is in 16-bit code units. Does not advance rPC. 243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The "_S" variant works the same but treats the value as signed. 245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) 247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) 248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Fetch one byte from an offset past the current PC. Pass in the same 251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "_count" as you would for FETCH, and an additional 0/1 indicating which 252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * byte of the halfword you want (lo/hi). 253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) 255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Put the instruction's opcode field into the specified register. 258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_INST_OPCODE(rd) and rd, rINST, 0xFF 260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Put the prefetched instruction's opcode field into the specified register. 263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_PREFETCHED_OPCODE(dreg, sreg) andi dreg, sreg, 255 265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Begin executing the opcode in rd. 268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GOTO_OPCODE(rd) sll rd, rd, 7; \ 270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rd, rIBASE, rd; \ 271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, rd 272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GOTO_OPCODE_BASE(_base, rd) sll rd, rd, 7; \ 274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rd, _base, rd; \ 275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, rd 276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Get/set the 32-bit value from a Dalvik register. 279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix) 281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \ 283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noat; l.s rd, (AT); .set at 284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG(rd, rix) .set noat; \ 286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rd, 0(t8); \ 289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 0(t8) 292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG64(rlo, rhi, rix) .set noat; \ 294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rlo, 0(t8); \ 297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rhi, 4(t8); \ 298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 0(t8); \ 301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 4(t8) 302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef FPU64 304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG64_F(rlo, rhi, rix) .set noat; \ 305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 0(t8); \ 308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 4(t8); \ 309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhc1 AT, rlo; \ 311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw AT, 4(t8); \ 312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s.s rlo, 0(t8) 314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG64_F(rlo, rhi, rix) .set noat; \ 316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s.s rlo, 0(t8); \ 319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s.s rhi, 4(t8); \ 320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 0(t8); \ 323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 4(t8) 324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG_OBJECT(rd, rix) .set noat; \ 327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rd, 0(t8); \ 330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rd, 0(t8) 333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Combination of the SET_VREG and GOTO_OPCODE functions to save 1 instruction */ 335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG_GOTO(rd, rix, dst) .set noreorder; \ 336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll dst, dst, 7; \ 337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu dst, rIBASE, dst; \ 338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noat; \ 339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rd, 0(t8); \ 342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, dst; \ 345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 0(t8); \ 346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set reorder 347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Combination of the SET_VREG64 and GOTO_OPCODE functions to save 1 instruction */ 349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG64_GOTO(rlo, rhi, rix, dst) .set noreorder; \ 350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll dst, dst, 7; \ 351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu dst, rIBASE, dst; \ 352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noat; \ 353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rlo, 0(t8); \ 356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rhi, 4(t8); \ 357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 0(t8); \ 360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, dst; \ 361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 4(t8); \ 362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set reorder 363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define SET_VREG_F(rd, rix) .set noat; \ 365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, rix, 2; \ 366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rFP, AT; \ 367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s.s rd, 0(t8); \ 368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t8, rREFS, AT; \ 369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at; \ 370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, 0(t8) 371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_OPA(rd) srl rd, rINST, 8 373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE2 374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_OPA4(rd) ext rd, rINST, 8, 4 375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_OPA4(rd) GET_OPA(rd); and rd, 0xf 377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define GET_OPB(rd) srl rd, rINST, 12 379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Form an Effective Address rd = rbase + roff<<n; 382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Uses reg AT 383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define EASN(rd, rbase, roff, rshift) .set noat; \ 385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll AT, roff, rshift; \ 386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rd, rbase, AT; \ 387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at 388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define EAS1(rd, rbase, roff) EASN(rd, rbase, roff, 1) 390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define EAS2(rd, rbase, roff) EASN(rd, rbase, roff, 2) 391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define EAS3(rd, rbase, roff) EASN(rd, rbase, roff, 3) 392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define EAS4(rd, rbase, roff) EASN(rd, rbase, roff, 4) 393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Form an Effective Shift Right rd = rbase + roff>>n; 396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Uses reg AT 397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define ESRN(rd, rbase, roff, rshift) .set noat; \ 399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl AT, roff, rshift; \ 400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rd, rbase, AT; \ 401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at 402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD_eas2(rd, rbase, roff) EAS2(AT, rbase, roff); \ 404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noat; lw rd, 0(AT); .set at 405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STORE_eas2(rd, rbase, roff) EAS2(AT, rbase, roff); \ 407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noat; sw rd, 0(AT); .set at 408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD_RB_OFF(rd, rbase, off) lw rd, off(rbase) 410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STORE_RB_OFF(rd, rbase, off) sw rd, off(rbase) 411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STORE64_off(rlo, rhi, rbase, off) sw rlo, off(rbase); \ 413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw rhi, (off+4)(rbase) 414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD64_off(rlo, rhi, rbase, off) lw rlo, off(rbase); \ 415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rhi, (off+4)(rbase) 416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STORE64(rlo, rhi, rbase) STORE64_off(rlo, rhi, rbase, 0) 418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD64(rlo, rhi, rbase) LOAD64_off(rlo, rhi, rbase, 0) 419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef FPU64 421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STORE64_off_F(rlo, rhi, rbase, off) s.s rlo, off(rbase); \ 422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noat; \ 423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhc1 AT, rlo; \ 424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw AT, (off+4)(rbase); \ 425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at 426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD64_off_F(rlo, rhi, rbase, off) l.s rlo, off(rbase); \ 427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noat; \ 428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw AT, (off+4)(rbase); \ 429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mthc1 AT, rlo; \ 430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set at 431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STORE64_off_F(rlo, rhi, rbase, off) s.s rlo, off(rbase); \ 433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung s.s rhi, (off+4)(rbase) 434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD64_off_F(rlo, rhi, rbase, off) l.s rlo, off(rbase); \ 435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s rhi, (off+4)(rbase) 436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0) 439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0) 440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET) 443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_STORE(rd, off) sw rd, off(sp) 445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_LOAD(rd, off) lw rd, off(sp) 446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define CREATE_STACK(n) subu sp, sp, n 447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define DELETE_STACK(n) addu sp, sp, n 448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD_ADDR(dest, addr) la dest, addr 450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define LOAD_IMM(dest, imm) li dest, imm 451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define MOVE_REG(dest, src) move dest, src 452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_SIZE 128 453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_OFFSET_ARG04 16 455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_OFFSET_ARG05 20 456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_OFFSET_ARG06 24 457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_OFFSET_ARG07 28 458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_OFFSET_GP 84 459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define JAL(n) jal n 461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define BAL(n) bal n 462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * FP register usage restrictions: 465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1) We don't use the callee save FP registers so we don't have to save them. 466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2) We don't use the odd FP registers so we can share code with mips32r6. 467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_STORE_FULL() CREATE_STACK(STACK_SIZE); \ 469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(ra, 124); \ 470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s8, 120); \ 471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s0, 116); \ 472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s1, 112); \ 473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s2, 108); \ 474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s3, 104); \ 475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s4, 100); \ 476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s5, 96); \ 477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s6, 92); \ 478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE(s7, 88); 479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#define STACK_LOAD_FULL() STACK_LOAD(gp, STACK_OFFSET_GP); \ 481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s7, 88); \ 482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s6, 92); \ 483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s5, 96); \ 484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s4, 100); \ 485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s3, 104); \ 486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s2, 108); \ 487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s1, 112); \ 488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s0, 116); \ 489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(s8, 120); \ 490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD(ra, 124); \ 491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung DELETE_STACK(STACK_SIZE) 492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/entry.S */ 494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Copyright (C) 2016 The Android Open Source Project 496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Licensed under the Apache License, Version 2.0 (the "License"); 498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * you may not use this file except in compliance with the License. 499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * You may obtain a copy of the License at 500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * http://www.apache.org/licenses/LICENSE-2.0 502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Unless required by applicable law or agreed to in writing, software 504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * distributed under the License is distributed on an "AS IS" BASIS, 505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * See the License for the specific language governing permissions and 507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * limitations under the License. 508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Interpreter entry point. 511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .text 514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .align 2 515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .global ExecuteMterpImpl 516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .ent ExecuteMterpImpl 517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .frame sp, STACK_SIZE, ra 518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * On entry: 520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a0 Thread* self 521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a1 code_item 522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a2 ShadowFrame 523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a3 JValue* result_register 524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungExecuteMterpImpl: 528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set noreorder 529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .cpload t9 530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .set reorder 531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Save to the stack. Frame size = STACK_SIZE */ 532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_STORE_FULL() 533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* This directive will make sure all subsequent jal restore gp at a known offset */ 534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .cprestore STACK_OFFSET_GP 535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* Remember the return register */ 537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) 538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* Remember the code_item */ 540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2) 541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* set up "named" registers */ 543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move rSELF, a0 544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) 545ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs. 546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(rREFS, rFP, a0) # point to reference array in shadow frame 547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc 548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rPC, a1, CODEITEM_INSNS_OFFSET # Point to base of insns[] 549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS1(rPC, rPC, a0) # Create direct pointer to 1st dex opcode 550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* Starting ibase */ 554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* start executing the instruction at rPC */ 557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_INST() # load rINST from rPC 558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* NOTE: no fallthrough */ 561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .global artMterpAsmInstructionStart 564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .type artMterpAsmInstructionStart, %function 565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungartMterpAsmInstructionStart = .L_op_nop 566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .text 567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_nop: /* 0x00 */ 571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_nop.S */ 572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move: /* 0x01 */ 579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move.S */ 580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for move, move-object, long-to-int */ 581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vA, vB */ 582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B from 15:12 583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A from 11:8 584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[B] 586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # t0 <- opcode from rINST 587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a2, a0) # fp[A] <- a2 589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a2, a0) # fp[A] <- a2 591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_from16: /* 0x02 */ 597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_from16.S */ 598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for: move/from16, move-object/from16 */ 599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBBBB */ 600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- BBBB 601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[BBBB] 604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a2, a0) # fp[AA] <- a2 607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a2, a0) # fp[AA] <- a2 609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_16: /* 0x03 */ 615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_16.S */ 616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for: move/16, move-object/16 */ 617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAAAA, vBBBB */ 618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB 619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- AAAA 620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[BBBB] 622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a2, a0) # fp[AAAA] <- a2 625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a2, a0) # fp[AAAA] <- a2 627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_wide: /* 0x04 */ 633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_wide.S */ 634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* move-wide vA, vB */ 635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- fp[B] 640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a2) # fp[A] <- a0/a1 642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_wide_from16: /* 0x05 */ 648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_wide_from16.S */ 649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* move-wide/from16 vAA, vBBBB */ 650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a3, 1) # a3 <- BBBB 652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] 654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] 655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a2) # fp[AA] <- a0/a1 657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_wide_16: /* 0x06 */ 663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_wide_16.S */ 664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* move-wide/16 vAAAA, vBBBB */ 665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a3, 2) # a3 <- BBBB 667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a2, 1) # a2 <- AAAA 668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] 669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] 670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a2) # fp[AAAA] <- a0/a1 672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_object: /* 0x07 */ 678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_object.S */ 679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move.S */ 680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for move, move-object, long-to-int */ 681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vA, vB */ 682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B from 15:12 683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A from 11:8 684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[B] 686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # t0 <- opcode from rINST 687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a2, a0) # fp[A] <- a2 689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a2, a0) # fp[A] <- a2 691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_object_from16: /* 0x08 */ 698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_object_from16.S */ 699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_from16.S */ 700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for: move/from16, move-object/from16 */ 701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBBBB */ 702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- BBBB 703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[BBBB] 706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a2, a0) # fp[AA] <- a2 709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a2, a0) # fp[AA] <- a2 711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_object_16: /* 0x09 */ 718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_object_16.S */ 719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_16.S */ 720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for: move/16, move-object/16 */ 721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAAAA, vBBBB */ 722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB 723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- AAAA 724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[BBBB] 726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a2, a0) # fp[AAAA] <- a2 729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a2, a0) # fp[AAAA] <- a2 731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_result: /* 0x0a */ 738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_result.S */ 739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for: move-result, move-result-object */ 740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA */ 741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, 0(a0) # a0 <- result.i 745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a0, a2) # fp[AA] <- a0 748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a0, a2) # fp[AA] <- a0 750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_result_wide: /* 0x0b */ 756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_result_wide.S */ 757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* move-result-wide vAA */ 758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- retval.j 761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a2) # fp[AA] <- a0/a1 763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_result_object: /* 0x0c */ 769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_result_object.S */ 770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_result.S */ 771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for: move-result, move-result-object */ 772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA */ 773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, 0(a0) # a0 <- result.i 777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a0, a2) # fp[AA] <- a0 780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a0, a2) # fp[AA] <- a0 782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_move_exception: /* 0x0d */ 789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move_exception.S */ 790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* move-exception vAA */ 791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj 793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a3, a2) # fp[AA] <- exception obj 795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception 797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_return_void: /* 0x0e */ 802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_return_void.S */ 803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpThreadFenceForConstructor 804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpThreadFenceForConstructor) 805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz ra, 1f 809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpSuspendCheck) # (self) 810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move v0, zero 812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move v1, zero 813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpReturn 814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_return: /* 0x0f */ 818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_return.S */ 819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Return a 32-bit value. 821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: return, return-object 823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA */ 825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpThreadFenceForConstructor 826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpThreadFenceForConstructor) 827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz ra, 1f 831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpSuspendCheck) # (self) 832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(v0, a2) # v0 <- vAA 835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move v1, zero 836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpReturn 837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_return_wide: /* 0x10 */ 841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_return_wide.S */ 842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Return a 64-bit value. 844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* return-wide vAA */ 846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpThreadFenceForConstructor 847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpThreadFenceForConstructor) 848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz ra, 1f 852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpSuspendCheck) # (self) 853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[AA] 856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(v0, v1, a2) # v0/v1 <- vAA/vAA+1 857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpReturn 858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_return_object: /* 0x11 */ 862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_return_object.S */ 863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_return.S */ 864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Return a 32-bit value. 866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: return, return-object 868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA */ 870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpThreadFenceForConstructor 871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpThreadFenceForConstructor) 872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz ra, 1f 876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpSuspendCheck) # (self) 877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(v0, a2) # v0 <- vAA 880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move v1, zero 881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpReturn 882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_4: /* 0x12 */ 887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_4.S */ 888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const/4 vA, /* +B */ 889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, rINST, 16 # a1 <- Bxxx0000 890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- A+ 891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a1, 28 # a1 <- sssssssB (sign-extended) 893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, a0, 15 894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1 896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_16: /* 0x13 */ 900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_16.S */ 901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const/16 vAA, /* +BBBB */ 902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) 903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const: /* 0x14 */ 911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const.S */ 912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const vAA, /* +BBBBbbbb */ 913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (low) 915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB (high) 916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a1, 16 918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a1, a0 # a0 <- BBBBbbbb 919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_high16: /* 0x15 */ 925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_high16.S */ 926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const/high16 vAA, /* +BBBB0000 */ 927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) 928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, a0, 16 # a0 <- BBBB0000 930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_wide_16: /* 0x16 */ 937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_wide_16.S */ 938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const-wide/16 vAA, /* +BBBB */ 939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) 940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a0, 31 # a1 <- ssssssss 942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a3) # vAA <- a0/a1 945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_wide_32: /* 0x17 */ 950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_wide_32.S */ 951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const-wide/32 vAA, /* +BBBBbbbb */ 952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- 0000bbbb (low) 953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a2, 2) # a2 <- ssssBBBB (high) 955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a2, a2, 16 957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a2 # a0 <- BBBBbbbb 958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a0, 31 # a1 <- ssssssss 959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a3) # vAA <- a0/a1 961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_wide: /* 0x18 */ 966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_wide.S */ 967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const-wide vAA, /* +HHHHhhhhBBBBbbbb */ 968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (low) 969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB (low middle) 970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a2, 3) # a2 <- hhhh (high middle) 971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, 16 # 972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a1 # a0 <- BBBBbbbb (low word) 973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a3, 4) # a3 <- HHHH (high) 974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(t1) # t1 <- AA 975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a3, 16 976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a1, a3, a2 # a1 <- HHHHhhhh (high word) 977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(5) # advance rPC, load rINST 978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, t1) # vAA <- a0/a1 980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_wide_high16: /* 0x19 */ 985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_wide_high16.S */ 986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const-wide/high16 vAA, /* +BBBB000000000000 */ 987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) 988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li a0, 0 # a0 <- 00000000 990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, 16 # a1 <- BBBB0000 991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a3) # vAA <- a0/a1 994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_string: /* 0x1a */ 999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_string.S */ 1000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const/string vAA, String /* BBBB */ 1001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- BBBB 1003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a1) # a1 <- AA 1004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame 1005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF 1006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) 1007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 1008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException 1009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 1010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_string_jumbo: /* 0x1b */ 1016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_string_jumbo.S */ 1017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const/string vAA, String /* BBBBBBBB */ 1018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (low) 1020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a2, 2) # a2 <- BBBB (high) 1021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a1) # a1 <- AA 1022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a2, a2, 16 1023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a2 # a0 <- BBBBbbbb 1024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame 1025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF 1026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) 1027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(3) # load rINST 1028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException 1029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(3) # advance rPC 1030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_const_class: /* 0x1c */ 1036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_const_class.S */ 1037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # const/class vAA, Class /* BBBB */ 1038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- BBBB 1040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a1) # a1 <- AA 1041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame 1042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF 1043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpConstClass) 1044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 1045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException 1046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 1047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_monitor_enter: /* 0x1d */ 1053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_monitor_enter.S */ 1054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Synchronize on an object. 1056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* monitor-enter vAA */ 1058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 1060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vAA (object) 1061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rSELF # a1 <- self 1062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artLockObjectFromCode) # v0 <- artLockObject(obj, self) 1063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException 1064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_monitor_exit: /* 0x1e */ 1071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_monitor_exit.S */ 1072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Unlock an object. 1074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Exceptions that occur when unlocking a monitor need to appear as 1076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * if they happened at the following instruction. See the Dalvik 1077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * instruction spec. 1078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* monitor-exit vAA */ 1080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 1082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vAA (object) 1083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rSELF # a1 <- self 1084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self) 1085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException 1086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_check_cast: /* 0x1f */ 1093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_check_cast.S */ 1094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Check to see if a cast from one class to another is allowed. 1096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check-cast vAA, class /* BBBB */ 1098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- BBBB 1100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a1) # a1 <- AA 1101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &object 1102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- method 1103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 1104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpCheckCast) # v0 <- CheckCast(index, &obj, method, self) 1105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) 1106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException 1107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) 1108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_instance_of: /* 0x20 */ 1114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_instance_of.S */ 1115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Check to see if an object reference is an instance of a class. 1117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Most common situation is a non-null object, being compared against 1119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * an already-resolved class. 1120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # instance-of vA, vB, class /* CCCC */ 1122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCCC 1124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &object 1126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- method 1127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 1128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 1129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self) 1130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, THREAD_EXCEPTION_OFFSET(rSELF) 1131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 1132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a1, MterpException 1133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 1134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0 1136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_array_length: /* 0x21 */ 1140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_array_length.S */ 1141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Return the length of an array. 1143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A+ 1146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a1) # a0 <- vB (object ref) 1147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is object null? 1148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yup, fail 1149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length 1151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a3, a2, t0) # vA <- length 1153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_new_instance: /* 0x22 */ 1157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_new_instance.S */ 1158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Create a new instance of a class. 1160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # new-instance vAA, class /* BBBB */ 1162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME 1164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rSELF 1165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpNewInstance) 1167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpPossibleException 1168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_new_array: /* 0x23 */ 1175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_new_array.S */ 1176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Allocate an array of objects, specified with the array class 1178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and a count. 1179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The verifier guarantees that this is an array class, so we don't 1181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * check for it here. 1182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* new-array vA, vB, class@CCCC */ 1184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME 1186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rPC 1187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF 1189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpNewArray) 1190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpPossibleException 1191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_filled_new_array: /* 0x24 */ 1198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_filled_new_array.S */ 1199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Create a new array with elements filled from registers. 1201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: filled-new-array, filled-new-array/range 1203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 1205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, type /* BBBB */ 1206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpFilledNewArray 1207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame 1209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rPC 1210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF 1211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpFilledNewArray) # v0 <- helper(shadow_frame, pc, self) 1212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpPossibleException # has exception 1213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_filled_new_array_range: /* 0x25 */ 1220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_filled_new_array_range.S */ 1221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_filled_new_array.S */ 1222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Create a new array with elements filled from registers. 1224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: filled-new-array, filled-new-array/range 1226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 1228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, type /* BBBB */ 1229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpFilledNewArrayRange 1230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame 1232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rPC 1233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF 1234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpFilledNewArrayRange) # v0 <- helper(shadow_frame, pc, self) 1235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpPossibleException # has exception 1236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_fill_array_data: /* 0x26 */ 1244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_fill_array_data.S */ 1245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* fill-array-data vAA, +BBBBBBBB */ 1246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (lo) 1248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB (hi) 1249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 1250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a1, 16 # a1 <- BBBBbbbb 1251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a1, a0, a1 # a1 <- BBBBbbbb 1252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vAA (array object) 1253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.) 1254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpFillArrayData) # v0 <- Mterp(obj, payload) 1255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpPossibleException # has exception 1256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_throw: /* 0x27 */ 1263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_throw.S */ 1264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Throw an exception object in the current thread. 1266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* throw vAA */ 1268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() # exception handler can throw 1269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 1270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a2) # a1 <- vAA (exception object) 1271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null object? 1272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errNullObject # yes, throw an NPE instead 1273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw a1, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj 1274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpException 1275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_goto: /* 0x28 */ 1279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_goto.S */ 1280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Unconditional branch, 8-bit offset. 1282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The branch distance is a signed code-unit offset, which we need to 1284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * double to get a byte offset. 1285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* goto +AA */ 1287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, rINST, 16 # a0 <- AAxx0000 1289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) 1290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # a2 <- byte offset 1297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* If backwards branch refresh rIBASE */ 1299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a2, 1f 1300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, rINST, 16 # a0 <- AAxx0000 1307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) 1308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # a2 <- byte offset 1309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* If backwards branch refresh rIBASE */ 1311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 1f 1312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_goto_16: /* 0x29 */ 1322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_goto_16.S */ 1323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Unconditional branch, 16-bit offset. 1325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The branch distance is a signed code-unit offset, which we need to 1327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * double to get a byte offset. 1328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* goto/16 +AAAA */ 1330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) 1332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset, flags set 1339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 1f 1341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) 1348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset, flags set 1349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 1f 1351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_goto_32: /* 0x2a */ 1361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_goto_32.S */ 1362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Unconditional branch, 32-bit offset. 1364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The branch distance is a signed code-unit offset, which we need to 1366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * double to get a byte offset. 1367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Unlike most opcodes, this one is allowed to branch to itself, so 1369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * our "backward branch" test must be "<=0" instead of "<0". 1370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* goto/32 +AAAAAAAA */ 1372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- aaaa (lo) 1374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- AAAA (hi) 1375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a1, 16 1376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or rINST, a0, a1 # rINST <- AAAAaaaa 1377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset 1384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgtz a1, 1f 1386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- aaaa (lo) 1393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- AAAA (hi) 1394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a1, 16 1395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or rINST, a0, a1 # rINST <- AAAAaaaa 1396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset 1397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgtz a1, 1f 1399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_packed_switch: /* 0x2b */ 1409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_packed_switch.S */ 1410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Handle a packed-switch or sparse-switch instruction. In both cases 1412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * we decode it and hand it off to a helper function. 1413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * We don't really expect backward branches in a switch statement, but 1415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * they're perfectly legal, so we check for them here. 1416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: packed-switch, sparse-switch 1418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, +BBBB */ 1420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (lo) 1422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB (hi) 1423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 1424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll t0, a1, 16 1425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, t0 # a0 <- BBBBbbbb 1426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vAA 1427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset 1429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move rINST, v0 1430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset 1437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgtz a1, .Lop_packed_switch_finish 1439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (lo) 1443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB (hi) 1444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 1445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll t0, a1, 16 1446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, t0 # a0 <- BBBBbbbb 1447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vAA 1448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset 1450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move rINST, v0 1451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset 1452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgtz a1, 1f 1454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sparse_switch: /* 0x2c */ 1465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sparse_switch.S */ 1466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_packed_switch.S */ 1467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Handle a packed-switch or sparse-switch instruction. In both cases 1469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * we decode it and hand it off to a helper function. 1470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * We don't really expect backward branches in a switch statement, but 1472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * they're perfectly legal, so we check for them here. 1473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: packed-switch, sparse-switch 1475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, +BBBB */ 1477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (lo) 1479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB (hi) 1480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 1481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll t0, a1, 16 1482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, t0 # a0 <- BBBBbbbb 1483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vAA 1484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset 1486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move rINST, v0 1487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset 1494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgtz a1, .Lop_sparse_switch_finish 1496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- bbbb (lo) 1500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 2) # a1 <- BBBB (hi) 1501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 1502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll t0, a1, 16 1503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, t0 # a0 <- BBBBbbbb 1504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vAA 1505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset 1507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move rINST, v0 1508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # a1 <- byte offset 1509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 1510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgtz a1, 1f 1511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 1516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_cmpl_float: /* 0x2d */ 1523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_cmpl_float.S */ 1524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Compare two floating-point values. Puts 0, 1, or -1 into the 1526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * destination register rTEMP based on the results of the comparison. 1527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending 1529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * on what value we'd like to return when one of the operands is NaN. 1530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The operation we're implementing is: 1532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * if (x == y) 1533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return 0; 1534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * else if (x < y) 1535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return -1; 1536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * else if (x > y) 1537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return 1; 1538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * else 1539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return {-1 or 1}; // one or both operands was NaN 1540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: cmpl-float, cmpg-float 1542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 1544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* "clasic" form */ 1546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 1547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 1548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 1549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(ft0, a2) 1550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(ft1, a3) 1551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 1552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.s ft2, ft0, ft1 # Is ft0 < ft1 1553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpl_float_finish 1555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.s ft2, ft1, ft0 1556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpl_float_finish 1558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.eq.s ft2, ft0, ft1 1559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpl_float_finish 1561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpl_float_nan 1562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1 1564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpl_float_finish 1566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.s fcc0, ft1, ft0 1567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpl_float_finish 1569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.eq.s fcc0, ft0, ft1 1570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpl_float_finish 1572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpl_float_nan 1573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_cmpg_float: /* 0x2e */ 1578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_cmpg_float.S */ 1579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_cmpl_float.S */ 1580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Compare two floating-point values. Puts 0, 1, or -1 into the 1582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * destination register rTEMP based on the results of the comparison. 1583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending 1585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * on what value we'd like to return when one of the operands is NaN. 1586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The operation we're implementing is: 1588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * if (x == y) 1589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return 0; 1590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * else if (x < y) 1591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return -1; 1592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * else if (x > y) 1593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return 1; 1594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * else 1595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * return {-1 or 1}; // one or both operands was NaN 1596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: cmpl-float, cmpg-float 1598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 1600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* "clasic" form */ 1602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 1603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 1604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 1605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(ft0, a2) 1606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(ft1, a3) 1607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 1608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.s ft2, ft0, ft1 # Is ft0 < ft1 1609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpg_float_finish 1611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.s ft2, ft1, ft0 1612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpg_float_finish 1614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.eq.s ft2, ft0, ft1 1615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpg_float_finish 1617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpg_float_nan 1618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1 1620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpg_float_finish 1622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.s fcc0, ft1, ft0 1623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpg_float_finish 1625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.eq.s fcc0, ft0, ft1 1626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpg_float_finish 1628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpg_float_nan 1629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_cmpl_double: /* 0x2f */ 1635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_cmpl_double.S */ 1636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) 1638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * into the destination register (rTEMP) based on the comparison results. 1639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending 1641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * on what value we'd like to return when one of the operands is NaN. 1642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * See op_cmpl_float for more details. 1644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: cmpl-double, cmpg-double 1646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 1648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 1650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, a0, 255 # s5 <- BB 1651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl t0, a0, 8 # t0 <- CC 1652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[BB] 1653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, t0) # t0 <- &fp[CC] 1654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(ft0, ft0f, rOBJ) 1655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(ft1, ft1f, t0) 1656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 1657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.d ft2, ft0, ft1 1658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpl_double_finish 1660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.d ft2, ft1, ft0 1661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpl_double_finish 1663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.eq.d ft2, ft0, ft1 1664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpl_double_finish 1666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpl_double_nan 1667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.d fcc0, ft0, ft1 1669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpl_double_finish 1671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.d fcc0, ft1, ft0 1672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpl_double_finish 1674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.eq.d fcc0, ft0, ft1 1675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpl_double_finish 1677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpl_double_nan 1678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_cmpg_double: /* 0x30 */ 1683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_cmpg_double.S */ 1684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_cmpl_double.S */ 1685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) 1687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * into the destination register (rTEMP) based on the comparison results. 1688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending 1690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * on what value we'd like to return when one of the operands is NaN. 1691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * See op_cmpl_float for more details. 1693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: cmpl-double, cmpg-double 1695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 1697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 1699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, a0, 255 # s5 <- BB 1700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl t0, a0, 8 # t0 <- CC 1701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(rOBJ, rFP, rOBJ) # s5 <- &fp[BB] 1702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, t0) # t0 <- &fp[CC] 1703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(ft0, ft0f, rOBJ) 1704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(ft1, ft1f, t0) 1705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 1706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.d ft2, ft0, ft1 1707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpg_double_finish 1709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ult.d ft2, ft1, ft0 1710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpg_double_finish 1712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.eq.d ft2, ft0, ft1 1713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_cmpg_double_finish 1715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpg_double_nan 1716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 1717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.d fcc0, ft0, ft1 1718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 1719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpg_double_finish 1720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.olt.d fcc0, ft1, ft0 1721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 1722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpg_double_finish 1723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.eq.d fcc0, ft0, ft1 1724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 0 1725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t fcc0, .Lop_cmpg_double_finish 1726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_cmpg_double_nan 1727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_cmp_long: /* 0x31 */ 1733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_cmp_long.S */ 1734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Compare two 64-bit values 1736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * x = y return 0 1737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * x < y return -1 1738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * x > y return 1 1739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * I think I can improve on the ARM code by the following observation 1741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 1742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 1743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] 1744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* cmp-long vAA, vBB, vCC */ 1746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 1747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 1748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 1749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 1750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 1751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[CC] 1752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 1753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 1754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung slt t0, a1, a3 # compare hi 1757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sgt t1, a1, a3 1758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu v0, t1, t0 # v0 <- (-1, 1, 0) 1759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, .Lop_cmp_long_finish 1760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # at this point x.hi==y.hi 1761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sltu t0, a0, a2 # compare lo 1762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sgtu t1, a0, a2 1763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] 1764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmp_long_finish: 1766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 1768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_eq: /* 0x32 */ 1772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_eq.S */ 1773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/bincmp.S */ 1774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 1777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 1778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vA, vB, +CCCC */ 1782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A+ 1783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a1) # a3 <- vB 1785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vA 1786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bne a2, a3, 1f # branch to 1 if comparison failed 1787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 1789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 1791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 1792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # convert to bytes 1801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a2, .L_op_if_eq_finish 1803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_ne: /* 0x33 */ 1811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_ne.S */ 1812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/bincmp.S */ 1813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 1816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 1817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vA, vB, +CCCC */ 1821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A+ 1822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a1) # a3 <- vB 1824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vA 1825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beq a2, a3, 1f # branch to 1 if comparison failed 1826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 1828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 1830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 1831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # convert to bytes 1840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a2, .L_op_if_ne_finish 1842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_lt: /* 0x34 */ 1850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_lt.S */ 1851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/bincmp.S */ 1852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 1855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 1856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vA, vB, +CCCC */ 1860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A+ 1861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a1) # a3 <- vB 1863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vA 1864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bge a2, a3, 1f # branch to 1 if comparison failed 1865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 1867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 1869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 1870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # convert to bytes 1879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a2, .L_op_if_lt_finish 1881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_ge: /* 0x35 */ 1889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_ge.S */ 1890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/bincmp.S */ 1891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 1894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 1895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vA, vB, +CCCC */ 1899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A+ 1900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a1) # a3 <- vB 1902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vA 1903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung blt a2, a3, 1f # branch to 1 if comparison failed 1904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 1906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 1908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 1909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # convert to bytes 1918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a2, .L_op_if_ge_finish 1920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_gt: /* 0x36 */ 1928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_gt.S */ 1929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/bincmp.S */ 1930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 1933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 1934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vA, vB, +CCCC */ 1938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A+ 1939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a1) # a3 <- vB 1941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vA 1942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ble a2, a3, 1f # branch to 1 if comparison failed 1943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 1945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 1947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 1948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # convert to bytes 1957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a2, .L_op_if_gt_finish 1959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 1961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 1964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 1965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 1966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_le: /* 0x37 */ 1967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_le.S */ 1968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/bincmp.S */ 1969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 1970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 1972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 1973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 1974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 1976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vA, vB, +CCCC */ 1977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A+ 1978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 1979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a1) # a3 <- vB 1980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vA 1981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgt a2, a3, 1f # branch to 1 if comparison failed 1982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 1984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 1985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 1986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 1987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 1988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 1989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 1990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 1991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 1992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 1993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 1994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 1995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, rINST, rINST # convert to bytes 1996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 1997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a2, .L_op_if_le_finish 1998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 1999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 2000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_eqz: /* 0x38 */ 2006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_eqz.S */ 2007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/zcmp.S */ 2008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 2011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 2012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vAA, +BBBB */ 2016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 2017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vAA 2018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bne a2, zero, 1f # branch to 1 if comparison failed 2020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 2021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 2022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 2023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 2024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 2025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 2027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 2028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 2029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 2030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 2031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 2032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # convert to bytes 2033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 3f 2035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 2036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 2037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung3: 2038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_nez: /* 0x39 */ 2045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_nez.S */ 2046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/zcmp.S */ 2047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 2050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 2051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vAA, +BBBB */ 2055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 2056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vAA 2057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beq a2, zero, 1f # branch to 1 if comparison failed 2059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 2060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 2061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 2062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 2063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 2064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 2066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 2067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 2068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 2069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 2070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 2071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # convert to bytes 2072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 3f 2074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 2075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 2076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung3: 2077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_ltz: /* 0x3a */ 2084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_ltz.S */ 2085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/zcmp.S */ 2086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 2089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 2090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vAA, +BBBB */ 2094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 2095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vAA 2096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bge a2, zero, 1f # branch to 1 if comparison failed 2098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 2099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 2100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 2101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 2102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 2103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 2105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 2106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 2107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 2108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 2109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 2110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # convert to bytes 2111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 3f 2113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 2114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 2115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung3: 2116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_gez: /* 0x3b */ 2123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_gez.S */ 2124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/zcmp.S */ 2125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 2128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 2129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vAA, +BBBB */ 2133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 2134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vAA 2135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung blt a2, zero, 1f # branch to 1 if comparison failed 2137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 2138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 2139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 2140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 2141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 2142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 2144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 2145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 2146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 2147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 2148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 2149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # convert to bytes 2150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 3f 2152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 2153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 2154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung3: 2155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_gtz: /* 0x3c */ 2162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_gtz.S */ 2163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/zcmp.S */ 2164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 2167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 2168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vAA, +BBBB */ 2172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 2173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vAA 2174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ble a2, zero, 1f # branch to 1 if comparison failed 2176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 2177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 2178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 2179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 2180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 2181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 2183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 2184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 2185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 2186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 2187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 2188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # convert to bytes 2189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 3f 2191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 2192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 2193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung3: 2194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_lez: /* 0x3d */ 2201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_if_lez.S */ 2202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/zcmp.S */ 2203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic one-operand compare-and-branch operation. Provide a "revcmp" 2205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * fragment that specifies the *reverse* comparison to perform, e.g. 2206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for "if-le" you would use "gt". 2207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* if-cmp vAA, +BBBB */ 2211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 2212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vAA 2213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgt a2, zero, 1f # branch to 1 if comparison failed 2215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b 2f 2216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 2217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rINST, 2 # rINST- BYTE branch dist for not-taken 2218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung2: 2219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_PROFILE_BRANCHES 2220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 2222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 2223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 2224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpProfileBranch) # (self, shadow_frame, offset) 2225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 2226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 2227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rINST, rINST # convert to bytes 2228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 2229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgez a1, 3f 2230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 2231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCheckSuspendAndContinue 2232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung3: 2233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_3e: /* 0x3e */ 2240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_3e.S */ 2241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 2242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 2243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 2244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 2246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_3f: /* 0x3f */ 2251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_3f.S */ 2252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 2253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 2254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 2255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 2257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_40: /* 0x40 */ 2262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_40.S */ 2263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 2264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 2265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 2266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 2268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_41: /* 0x41 */ 2273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_41.S */ 2274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 2275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 2276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 2277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 2279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_42: /* 0x42 */ 2284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_42.S */ 2285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 2286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 2287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 2288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 2290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_43: /* 0x43 */ 2295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_43.S */ 2296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 2297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 2298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 2299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 2301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aget: /* 0x44 */ 2306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget.S */ 2307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array get, 32 bits or less. vAA <- vBB[vCC]. 2309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * instructions. We use a pair of FETCH_Bs instead. 2312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: assumes data offset for arrays is the same for all non-wide types. 2316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 2 2328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width 2329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # a1 >= a3; compare unsigned index 2333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aget_wide: /* 0x45 */ 2342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget_wide.S */ 2343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array get, 64 bits. vAA <- vBB[vCC]. 2345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Arrays of long/double are 64-bit aligned. 2347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* aget-wide vAA, vBB, vCC */ 2349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 2350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 2352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 2353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS3(a0, a0, a1) # a0 <- arrayObj + index*width 2359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) 2363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 2365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aget_object: /* 0x46 */ 2369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget_object.S */ 2370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array object get. vAA <- vBB[vCC]. 2372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aget-object 2374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) 2383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, THREAD_EXCEPTION_OFFSET(rSELF) 2384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a1, MterpException 2386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, rOBJ) # vAA <- v0 2387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aget_boolean: /* 0x47 */ 2394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget_boolean.S */ 2395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget.S */ 2396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array get, 32 bits or less. vAA <- vBB[vCC]. 2398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * instructions. We use a pair of FETCH_Bs instead. 2401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: assumes data offset for arrays is the same for all non-wide types. 2405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # a1 >= a3; compare unsigned index 2422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aget_byte: /* 0x48 */ 2432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget_byte.S */ 2433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget.S */ 2434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array get, 32 bits or less. vAA <- vBB[vCC]. 2436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * instructions. We use a pair of FETCH_Bs instead. 2439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: assumes data offset for arrays is the same for all non-wide types. 2443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # a1 >= a3; compare unsigned index 2460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aget_char: /* 0x49 */ 2470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget_char.S */ 2471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget.S */ 2472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array get, 32 bits or less. vAA <- vBB[vCC]. 2474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * instructions. We use a pair of FETCH_Bs instead. 2477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: assumes data offset for arrays is the same for all non-wide types. 2481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 2493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # a1 >= a3; compare unsigned index 2498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aget_short: /* 0x4a */ 2508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget_short.S */ 2509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aget.S */ 2510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array get, 32 bits or less. vAA <- vBB[vCC]. 2512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * instructions. We use a pair of FETCH_Bs instead. 2515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: assumes data offset for arrays is the same for all non-wide types. 2519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 2531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # a1 >= a3; compare unsigned index 2536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aput: /* 0x4b */ 2546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput.S */ 2547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array put, 32 bits or less. vBB[vCC] <- vAA. 2550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 2 2566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width 2567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, rOBJ) # a2 <- vAA 2573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aput_wide: /* 0x4c */ 2580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput_wide.S */ 2581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array put, 64 bits. vBB[vCC] <- vAA. 2583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* aput-wide vAA, vBB, vCC */ 2587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 2588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(t0) # t0 <- AA 2589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 2590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 2591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS3(a0, a0, a1) # a0 <- arrayObj + index*width 2597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] 2598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # compare unsigned index, length 2599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 2603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] 2605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aput_object: /* 0x4d */ 2610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput_object.S */ 2611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Store an object into an array. vBB[vCC] <- vAA. 2613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME 2618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rPC 2619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 2620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpAputObject) 2621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpPossibleException 2622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aput_boolean: /* 0x4e */ 2629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput_boolean.S */ 2630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput.S */ 2631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array put, 32 bits or less. vBB[vCC] <- vAA. 2634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, rOBJ) # a2 <- vAA 2657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aput_byte: /* 0x4f */ 2665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput_byte.S */ 2666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput.S */ 2667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array put, 32 bits or less. vBB[vCC] <- vAA. 2670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, rOBJ) # a2 <- vAA 2693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aput_char: /* 0x50 */ 2701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput_char.S */ 2702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput.S */ 2703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array put, 32 bits or less. vBB[vCC] <- vAA. 2706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 2722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, rOBJ) # a2 <- vAA 2729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_aput_short: /* 0x51 */ 2737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput_short.S */ 2738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_aput.S */ 2739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Array put, 32 bits or less. vBB[vCC] <- vAA. 2742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If this changes, specialize. 2747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, vBB, vCC */ 2749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a2, 1, 0) # a2 <- BB 2750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 2751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_B(a3, 1, 1) # a3 <- CC 2752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB (array object) 2753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC (requested index) 2754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # null array object? 2755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, common_errNullObject # yes, bail 2756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 2758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 2761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bgeu a1, a3, common_errArrayIndex # index >= length, bail 2763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, rOBJ) # a2 <- vAA 2765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget: /* 0x52 */ 2773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget.S */ 2774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General instance field get. 2776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 2781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 2785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGet32InstanceFromCode) 2786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 2788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpPossibleException # bail out 2790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[A] <- v0 2792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[A] <- v0 2794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_wide: /* 0x53 */ 2802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_wide.S */ 2803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 64-bit instance field get. 2805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iget-wide 2807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field byte offset 2810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 2814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGet64InstanceFromCode) 2815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 2817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException # bail out 2819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, a2) # fp[A] <- v0/v1 2820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_object: /* 0x54 */ 2827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_object.S */ 2828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget.S */ 2829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General instance field get. 2831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 2836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 2840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetObjInstanceFromCode) 2841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 2843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpPossibleException # bail out 2845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 2846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[A] <- v0 2847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[A] <- v0 2849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_boolean: /* 0x55 */ 2858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_boolean.S */ 2859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget.S */ 2860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General instance field get. 2862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 2867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 2871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetBooleanInstanceFromCode) 2872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 2874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpPossibleException # bail out 2876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[A] <- v0 2878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[A] <- v0 2880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_byte: /* 0x56 */ 2889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_byte.S */ 2890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget.S */ 2891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General instance field get. 2893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 2898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 2902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetByteInstanceFromCode) 2903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 2905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpPossibleException # bail out 2907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[A] <- v0 2909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[A] <- v0 2911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_char: /* 0x57 */ 2920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_char.S */ 2921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget.S */ 2922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General instance field get. 2924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 2929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 2933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetCharInstanceFromCode) 2934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 2936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpPossibleException # bail out 2938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[A] <- v0 2940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[A] <- v0 2942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_short: /* 0x58 */ 2951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_short.S */ 2952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget.S */ 2953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General instance field get. 2955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 2960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 2964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetShortInstanceFromCode) 2965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 2967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpPossibleException # bail out 2969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 2970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[A] <- v0 2971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 2972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[A] <- v0 2973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 2974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 2975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 2976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 2977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 2979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 2980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 2981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput: /* 0x59 */ 2982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput.S */ 2983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General 32-bit instance field put. 2985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 2986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 2988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, field /* CCCC */ 2989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artSet32InstanceFromMterp 2990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 2991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 2992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 2993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A+ 2995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a2) # a2 <- fp[A] 2996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 2998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet32InstanceFromMterp) 2999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException # bail out 3000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_wide: /* 0x5a */ 3007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_wide.S */ 3008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # iput-wide vA, vB, field /* CCCC */ 3009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artSet64InstanceFromMterp 3010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 3012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 3013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 3014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A+ 3015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[A] 3016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 3017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet64InstanceFromMterp) 3019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException # bail out 3020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_object: /* 0x5b */ 3027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_object.S */ 3028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 32-bit instance field put. 3030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iput-object, iput-object-volatile 3032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, field /* CCCC */ 3034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME 3036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rPC 3037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 3038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF 3039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpIputObject) 3040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 3042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_boolean: /* 0x5c */ 3048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_boolean.S */ 3049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput.S */ 3050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General 32-bit instance field put. 3052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iput, iput-boolean, iput-byte, iput-char, iput-short 3054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, field /* CCCC */ 3056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artSet8InstanceFromMterp 3057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 3059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 3060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 3061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A+ 3062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a2) # a2 <- fp[A] 3063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 3064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet8InstanceFromMterp) 3066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException # bail out 3067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_byte: /* 0x5d */ 3075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_byte.S */ 3076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput.S */ 3077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General 32-bit instance field put. 3079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iput, iput-boolean, iput-byte, iput-char, iput-short 3081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, field /* CCCC */ 3083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artSet8InstanceFromMterp 3084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 3086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 3087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 3088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A+ 3089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a2) # a2 <- fp[A] 3090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 3091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet8InstanceFromMterp) 3093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException # bail out 3094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_char: /* 0x5e */ 3102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_char.S */ 3103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput.S */ 3104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General 32-bit instance field put. 3106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iput, iput-boolean, iput-byte, iput-char, iput-short 3108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, field /* CCCC */ 3110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artSet16InstanceFromMterp 3111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 3113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 3114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 3115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A+ 3116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a2) # a2 <- fp[A] 3117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 3118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet16InstanceFromMterp) 3120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException # bail out 3121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_short: /* 0x5f */ 3129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_short.S */ 3130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput.S */ 3131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General 32-bit instance field put. 3133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: iput, iput-boolean, iput-byte, iput-char, iput-short 3135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, field /* CCCC */ 3137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artSet16InstanceFromMterp 3138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 3140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 3141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 3142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A+ 3143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a2) # a2 <- fp[A] 3144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 3145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet16InstanceFromMterp) 3147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpPossibleException # bail out 3148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sget: /* 0x60 */ 3156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget.S */ 3157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SGET handler. 3159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artGet32StaticFromCode 3164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF # a2 <- self 3168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGet32StaticFromCode) 3169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 3171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) 3172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException # bail out 3173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.if 0 3174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0 3175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.else 3176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[AA] <- v0 3177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.endif 3178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) 3179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sget_wide: /* 0x61 */ 3185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget_wide.S */ 3186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 64-bit SGET handler. 3188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # sget-wide vAA, field /* BBBB */ 3190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artGet64StaticFromCode 3191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF # a2 <- self 3195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGet64StaticFromCode) 3196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException 3198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a1) # a1 <- AA 3199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 3200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, a1) # vAA/vAA+1 <- v0/v1 3201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sget_object: /* 0x62 */ 3207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget_object.S */ 3208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget.S */ 3209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SGET handler. 3211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artGetObjStaticFromCode 3216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF # a2 <- self 3220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetObjStaticFromCode) 3221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 3223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) 3224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException # bail out 3225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.if 1 3226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0 3227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.else 3228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[AA] <- v0 3229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.endif 3230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) 3231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sget_boolean: /* 0x63 */ 3238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget_boolean.S */ 3239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget.S */ 3240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SGET handler. 3242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artGetBooleanStaticFromCode 3247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF # a2 <- self 3251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetBooleanStaticFromCode) 3252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 3254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) 3255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException # bail out 3256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.if 0 3257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0 3258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.else 3259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[AA] <- v0 3260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.endif 3261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) 3262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sget_byte: /* 0x64 */ 3269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget_byte.S */ 3270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget.S */ 3271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SGET handler. 3273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artGetByteStaticFromCode 3278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF # a2 <- self 3282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetByteStaticFromCode) 3283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 3285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) 3286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException # bail out 3287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.if 0 3288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0 3289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.else 3290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[AA] <- v0 3291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.endif 3292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) 3293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sget_char: /* 0x65 */ 3300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget_char.S */ 3301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget.S */ 3302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SGET handler. 3304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artGetCharStaticFromCode 3309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF # a2 <- self 3313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetCharStaticFromCode) 3314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 3316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) 3317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException # bail out 3318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.if 0 3319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0 3320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.else 3321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[AA] <- v0 3322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.endif 3323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) 3324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sget_short: /* 0x66 */ 3331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget_short.S */ 3332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sget.S */ 3333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SGET handler. 3335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artGetShortStaticFromCode 3340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rSELF # a2 <- self 3344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artGetShortStaticFromCode) 3345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 3347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) 3348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpException # bail out 3349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.if 0 3350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[AA] <- v0 3351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.else 3352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(v0, a2) # fp[AA] <- v0 3353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.endif 3354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) 3355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sput: /* 0x67 */ 3362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput.S */ 3363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SPUT handler. 3365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 3372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 3375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet32StaticFromCode) 3377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException # bail out 3378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sput_wide: /* 0x68 */ 3385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput_wide.S */ 3386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 64-bit SPUT handler. 3388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # sput-wide vAA, field /* BBBB */ 3390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern artSet64IndirectStaticFromMterp 3391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref CCCC 3393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a2) # a2 <- AA 3395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[AA] 3396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 3397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet64IndirectStaticFromMterp) 3399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException # bail out 3400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sput_object: /* 0x69 */ 3407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput_object.S */ 3408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General 32-bit SPUT handler. 3410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sput-object, 3412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vAA, field@BBBB */ 3414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME 3416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rPC 3417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 3418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF 3419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpSputObject) 3420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 3422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sput_boolean: /* 0x6a */ 3428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput_boolean.S */ 3429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput.S */ 3430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SPUT handler. 3432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 3439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 3442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet8StaticFromCode) 3444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException # bail out 3445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sput_byte: /* 0x6b */ 3453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput_byte.S */ 3454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput.S */ 3455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SPUT handler. 3457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 3464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 3467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet8StaticFromCode) 3469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException # bail out 3470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sput_char: /* 0x6c */ 3478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput_char.S */ 3479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput.S */ 3480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SPUT handler. 3482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 3489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 3492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet16StaticFromCode) 3494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException # bail out 3495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sput_short: /* 0x6d */ 3503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput_short.S */ 3504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sput.S */ 3505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * General SPUT handler. 3507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vAA, field /* BBBB */ 3511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- field ref BBBB 3513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a3) # a3 <- AA 3514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rSELF # a3 <- self 3517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 3518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artSet16StaticFromCode) 3519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpException # bail out 3520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 3521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_virtual: /* 0x6e */ 3528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_virtual.S */ 3529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeVirtual 3536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeVirtual) 3542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_super: /* 0x6f */ 3553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_super.S */ 3554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeSuper 3561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeSuper) 3567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_direct: /* 0x70 */ 3578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_direct.S */ 3579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeDirect 3586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeDirect) 3592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_static: /* 0x71 */ 3603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_static.S */ 3604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeStatic 3611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeStatic) 3617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_interface: /* 0x72 */ 3628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_interface.S */ 3629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeInterface 3636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeInterface) 3642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_return_void_no_barrier: /* 0x73 */ 3653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_return_void_no_barrier.S */ 3654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw ra, THREAD_FLAGS_OFFSET(rSELF) 3655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 3657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz ra, 1f 3658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpSuspendCheck) # (self) 3659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 3660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move v0, zero 3661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move v1, zero 3662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpReturn 3663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_virtual_range: /* 0x74 */ 3667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_virtual_range.S */ 3668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeVirtualRange 3675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeVirtualRange) 3681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_super_range: /* 0x75 */ 3692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_super_range.S */ 3693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeSuperRange 3700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeSuperRange) 3706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_direct_range: /* 0x76 */ 3717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_direct_range.S */ 3718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeDirectRange 3725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeDirectRange) 3731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_static_range: /* 0x77 */ 3742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_static_range.S */ 3743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeStaticRange 3750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeStaticRange) 3756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_interface_range: /* 0x78 */ 3767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_interface_range.S */ 3768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 3769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 3771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 3773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 3774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeInterfaceRange 3775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 3776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 3777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 3778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 3779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 3780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeInterfaceRange) 3781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 3782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 3783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 3784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 3785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 3786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 3787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_79: /* 0x79 */ 3792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_79.S */ 3793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 3794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 3795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 3796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 3798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_7a: /* 0x7a */ 3803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_7a.S */ 3804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 3805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 3806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 3807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 3809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_neg_int: /* 0x7b */ 3814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_neg_int.S */ 3815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unop.S */ 3816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 3818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 3819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 3820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * int-to-byte, int-to-char, int-to-short 3823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 3825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 3826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t0) # t0 <- A+ 3827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vB 3828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 3830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung negu a0, a0 # a0 <- op, a0-a3 changed 3831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 3832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 3833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 9-10 instructions */ 3834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_not_int: /* 0x7c */ 3839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_not_int.S */ 3840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unop.S */ 3841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 3843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 3844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 3845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * int-to-byte, int-to-char, int-to-short 3848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 3850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 3851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t0) # t0 <- A+ 3852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vB 3853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 3855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not a0, a0 # a0 <- op, a0-a3 changed 3856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 3857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 3858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 9-10 instructions */ 3859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_neg_long: /* 0x7d */ 3864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_neg_long.S */ 3865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unopWide.S */ 3866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit unary operation. Provide an "instr" line that 3868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0/a1". 3869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be MIPS instruction or a function call. 3870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: neg-long, not-long, neg-double, 3872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 3874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 3875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 3876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 3877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- vAA 3878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung negu v0, a0 # optional op 3880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0 # a0/a1 <- op, a2-a3 changed 3881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, rOBJ) # vAA <- a0/a1 3883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-13 instructions */ 3885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_not_long: /* 0x7e */ 3890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_not_long.S */ 3891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unopWide.S */ 3892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit unary operation. Provide an "instr" line that 3894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0/a1". 3895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be MIPS instruction or a function call. 3896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: neg-long, not-long, neg-double, 3898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 3900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 3901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 3902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 3903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- vAA 3904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not a0, a0 # optional op 3906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not a1, a1 # a0/a1 <- op, a2-a3 changed 3907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, rOBJ) # vAA <- a0/a1 3909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-13 instructions */ 3911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_neg_float: /* 0x7f */ 3916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_neg_float.S */ 3917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unop.S */ 3918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 3920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 3921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 3922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * int-to-byte, int-to-char, int-to-short 3925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 3927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 3928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t0) # t0 <- A+ 3929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vB 3930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 3932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, 0x80000000 # a0 <- op, a0-a3 changed 3933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 3934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 3935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 9-10 instructions */ 3936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_neg_double: /* 0x80 */ 3941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_neg_double.S */ 3942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unopWide.S */ 3943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit unary operation. Provide an "instr" line that 3945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0/a1". 3946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be MIPS instruction or a function call. 3947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: neg-long, not-long, neg-double, 3949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 3951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 3952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 3953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 3954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- vAA 3955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 3957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, a1, 0x80000000 # a0/a1 <- op, a2-a3 changed 3958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, rOBJ) # vAA <- a0/a1 3960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-13 instructions */ 3962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_int_to_long: /* 0x81 */ 3967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_int_to_long.S */ 3968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unopWider.S */ 3969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = op a0", where 3972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "result" is a 64-bit quantity in a0/a1. 3973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: int-to-long 3975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 3976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 3977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 3978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 3979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vB 3980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 3982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a0, 31 # result <- op, a0-a3 changed 3983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 3984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, rOBJ) # vA/vA+1 <- a0/a1 3985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 3986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-11 instructions */ 3987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 3989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 3990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 3991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_int_to_float: /* 0x82 */ 3992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_int_to_float.S */ 3993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/funop.S */ 3994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 3996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 3997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 3998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 3999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: int-to-float, float-to-int 4000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t0 <- A+ 4004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a3) 4005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cvt.s.w fv0, fa0 4007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_int_to_float_set_vreg_f: 4009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) 4010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 4011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t1) # jump to next instruction 4012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_int_to_double: /* 0x83 */ 4017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_int_to_double.S */ 4018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/funopWider.S */ 4019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32bit-to-64bit unary operation. Provide an "instr" line 4021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = op a0", where 4022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "result" is a 64-bit quantity in a0/a1. 4023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: int-to-double, float-to-long, float-to-double 4025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 4028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a3) 4030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cvt.d.w fv0, fa0 4032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_int_to_double_set_vreg: 4034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1 4035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_long_to_int: /* 0x84 */ 4042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_long_to_int.S */ 4043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* we ignore the high word, making this equivalent to a 32-bit reg move */ 4044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_move.S */ 4045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* for move, move-object, long-to-int */ 4046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vA, vB */ 4047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B from 15:12 4048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A from 11:8 4049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[B] 4051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # t0 <- opcode from rINST 4052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(a2, a0) # fp[A] <- a2 4054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .else 4055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG(a2, a0) # fp[A] <- a2 4056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_long_to_float: /* 0x85 */ 4063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_long_to_float.S */ 4064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unopNarrower.S */ 4065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64bit-to-32bit unary operation. Provide an "instr" line 4067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = op a0/a1", where 4068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "result" is a 32-bit quantity in a0. 4069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: long-to-float, double-to-int, double-to-float 4071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If hard floating point support is available, use fa0 as the parameter, 4072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * except for long-to-float opcode. 4073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * (This would work for long-to-int, but that instruction is actually 4074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * an exact match for OP_MOVE.) 4075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 4079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 4080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(rARG0, rARG1, a3) 4081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__floatdisf) 4083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_long_to_float_set_vreg_f: 4085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vA <- result0 4086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_long_to_double: /* 0x86 */ 4093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_long_to_double.S */ 4094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/funopWide.S */ 4095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit unary operation. Provide an "instr" line that 4097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0/a1". 4098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 4099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * long-to-double, double-to-long 4101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 4104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 4106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(rARG0, rARG1, a3) 4107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed 4110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_long_to_double_set_vreg: 4112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) # vAA <- a0/a1 4113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-13 instructions */ 4116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_float_to_int: /* 0x87 */ 4121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_float_to_int.S */ 4122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/funop.S */ 4123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 4125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 4126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 4127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: int-to-float, float-to-int 4129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t0 <- A+ 4133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a3) 4134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b f2i_doconv 4136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_float_to_int_set_vreg_f: 4138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) 4139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 4140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t1) # jump to next instruction 4141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_float_to_long: /* 0x88 */ 4146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_float_to_long.S */ 4147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/funopWider.S */ 4148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32bit-to-64bit unary operation. Provide an "instr" line 4150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = op a0", where 4151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "result" is a 64-bit quantity in a0/a1. 4152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: int-to-double, float-to-long, float-to-double 4154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 4157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a3) 4159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b f2l_doconv 4161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_float_to_long_set_vreg: 4163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(rRESULT0, rRESULT1, rOBJ) # vA/vA+1 <- a0/a1 4164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_float_to_double: /* 0x89 */ 4171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_float_to_double.S */ 4172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/funopWider.S */ 4173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32bit-to-64bit unary operation. Provide an "instr" line 4175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = op a0", where 4176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "result" is a 64-bit quantity in a0/a1. 4177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: int-to-double, float-to-long, float-to-double 4179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 4182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a3) 4184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cvt.d.s fv0, fa0 4186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_float_to_double_set_vreg: 4188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) # vA/vA+1 <- a0/a1 4189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_double_to_int: /* 0x8a */ 4196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_double_to_int.S */ 4197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unopNarrower.S */ 4198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64bit-to-32bit unary operation. Provide an "instr" line 4200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = op a0/a1", where 4201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "result" is a 32-bit quantity in a0. 4202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: long-to-float, double-to-int, double-to-float 4204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If hard floating point support is available, use fa0 as the parameter, 4205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * except for long-to-float opcode. 4206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * (This would work for long-to-int, but that instruction is actually 4207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * an exact match for OP_MOVE.) 4208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 4212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 4213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a3) 4214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b d2i_doconv 4216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_double_to_int_set_vreg_f: 4218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vA <- result0 4219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 4223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Convert the double in a0/a1 to an int in a0. 4224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * We have to clip values to int min/max per the specification. The 4226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * expected common case is a "reasonable" value that converts directly 4227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * to modest integer. The EABI convert function isn't doing this for us. 4228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_double_to_long: /* 0x8b */ 4233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_double_to_long.S */ 4234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/funopWide.S */ 4235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit unary operation. Provide an "instr" line that 4237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0/a1". 4238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 4239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * long-to-double, double-to-long 4241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 4244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 4246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a3) 4247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b d2l_doconv # a0/a1 <- op, a2-a3 changed 4250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_double_to_long_set_vreg: 4252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(rRESULT0, rRESULT1, rOBJ) # vAA <- a0/a1 4253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-13 instructions */ 4256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_double_to_float: /* 0x8c */ 4261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_double_to_float.S */ 4262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unopNarrower.S */ 4263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64bit-to-32bit unary operation. Provide an "instr" line 4265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = op a0/a1", where 4266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * "result" is a 32-bit quantity in a0. 4267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: long-to-float, double-to-int, double-to-float 4269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If hard floating point support is available, use fa0 as the parameter, 4270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * except for long-to-float opcode. 4271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * (This would work for long-to-int, but that instruction is actually 4272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * an exact match for OP_MOVE.) 4273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 4277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[B] 4278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a3) 4279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cvt.s.d fv0, fa0 4281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_double_to_float_set_vreg_f: 4283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vA <- result0 4284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 4286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_int_to_byte: /* 0x8d */ 4291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_int_to_byte.S */ 4292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unop.S */ 4293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 4295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 4296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 4297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * int-to-byte, int-to-char, int-to-short 4300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t0) # t0 <- A+ 4304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vB 4305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, a0, 24 # optional op 4307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a0, a0, 24 # a0 <- op, a0-a3 changed 4308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 4309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 9-10 instructions */ 4311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_int_to_char: /* 0x8e */ 4316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_int_to_char.S */ 4317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unop.S */ 4318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 4320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 4321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 4322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * int-to-byte, int-to-char, int-to-short 4325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t0) # t0 <- A+ 4329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vB 4330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, 0xffff # a0 <- op, a0-a3 changed 4333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 4334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 9-10 instructions */ 4336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_int_to_short: /* 0x8f */ 4341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_int_to_short.S */ 4342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unop.S */ 4343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit unary operation. Provide an "instr" line that 4345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = op a0". 4346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. 4347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * int-to-byte, int-to-char, int-to-short 4350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* unop vA, vB */ 4352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 4353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t0) # t0 <- A+ 4354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a3) # a0 <- vB 4355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, 16 # optional op 4357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a0, 16 # a0 <- op, a0-a3 changed 4358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 4359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, t0, t1) # vAA <- result0 4360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 9-10 instructions */ 4361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_int: /* 0x90 */ 4366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_int.S */ 4367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4376ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4377ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 # a0 <- op, a0-a3 changed 4397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_int: /* 0x91 */ 4405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_int.S */ 4406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4415ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4416ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu a0, a0, a1 # a0 <- op, a0-a3 changed 4436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_int: /* 0x92 */ 4444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_int.S */ 4445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4454ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4455ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul a0, a0, a1 # a0 <- op, a0-a3 changed 4475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_int: /* 0x93 */ 4483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_int.S */ 4484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 4485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4494ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4495ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 4508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div a0, a0, a1 # a0 <- op, a0-a3 changed 4515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 4520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4529ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4530ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 4543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 4549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mflo a0 # a0 <- op, a0-a3 changed 4550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 4555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_int: /* 0x94 */ 4559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_int.S */ 4560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 4561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4570ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4571ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 4584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mod a0, a0, a1 # a0 <- op, a0-a3 changed 4591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 4596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4605ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4606ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 4619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 4625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhi a0 # a0 <- op, a0-a3 changed 4626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 4631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_and_int: /* 0x95 */ 4635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_and_int.S */ 4636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4645ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4646ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, a0, a1 # a0 <- op, a0-a3 changed 4666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_or_int: /* 0x96 */ 4674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_or_int.S */ 4675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4684ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4685ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a1 # a0 <- op, a0-a3 changed 4705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_xor_int: /* 0x97 */ 4713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_xor_int.S */ 4714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4723ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4724ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a0, a0, a1 # a0 <- op, a0-a3 changed 4744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shl_int: /* 0x98 */ 4752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shl_int.S */ 4753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4762ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4763ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, a0, a1 # a0 <- op, a0-a3 changed 4783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shr_int: /* 0x99 */ 4791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shr_int.S */ 4792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4801ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4802ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a0, a0, a1 # a0 <- op, a0-a3 changed 4822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_ushr_int: /* 0x9a */ 4830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_ushr_int.S */ 4831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop.S */ 4832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 4835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 4840ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4841ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee * correctly. 4842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 4845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 4852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 4853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 4855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 4856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 4860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, a0, a1 # a0 <- op, a0-a3 changed 4861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 4864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_long: /* 0x9b */ 4869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_long.S */ 4870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 4871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * The compiler generates the following sequence for 4872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * [v1 v0] = [a1 a0] + [a3 a2]; 4873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * addu v0,a2,a0 4874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * addu a1,a3,a1 4875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * sltu v1,v0,a2 4876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * addu v1,v1,a1 4877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide.S */ 4879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 4881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 4882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 4887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-long 4890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 4899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 4900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 4901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 4904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 4905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v0, a2, a0 # optional op 4909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed 4910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 4912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 14-17 instructions */ 4913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_long: /* 0x9c */ 4918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_long.S */ 4919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 4920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For little endian the code sequence looks as follows: 4921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * subu v0,a0,a2 4922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * subu v1,a1,a3 4923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * sltu a0,a0,v0 4924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * subu v1,v1,a0 4925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide.S */ 4927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 4929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 4930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 4931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 4932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 4934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 4935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-long 4938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 4939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 4942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 4944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 4945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 4946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 4947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 4948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 4949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 4951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 4952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 4953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 4954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu v0, a0, a2 # optional op 4957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed 4958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 4959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 4960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 14-17 instructions */ 4961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 4964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 4965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_long: /* 0x9d */ 4966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_long.S */ 4967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 4968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Signed 64-bit integer multiply. 4969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a1 a0 4970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * x a3 a2 4971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * ------------- 4972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a2a1 a2a0 4973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a3a0 4974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * a3a1 (<= unused) 4975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * --------------- 4976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * v1 v0 4977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 4978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* mul-long vAA, vBB, vCC */ 4979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 4980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and t0, a0, 255 # a2 <- BB 4981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl t1, a0, 8 # a3 <- CC 4982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, t0) # t0 <- &fp[BB] 4983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 4984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, t1) # t0 <- &fp[CC] 4986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 4988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul v1, a3, a0 # v1= a3a0 4989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 4990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mulu v0, a2, a0 # v0= a2a0 4991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung muhu t1, a2, a0 4992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 4993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung multu a2, a0 4994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhi t1 4995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mflo v0 # v0= a2a0 4996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 4997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul t0, a2, a1 # t0= a2a1 4998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v1, v1, t1 # v1+= hi(a2a0) 4999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v1, v1, t0 # v1= a3a0 + a2a1; 5000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(a0) # a0 <- AA 5002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_mul_long_finish 5004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_long: /* 0x9e */ 5008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_long.S */ 5009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide.S */ 5010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 5014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 5015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-long 5021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 5027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 5034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 5035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 5036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__divdi3) # result <- op, a0-a3 changed 5041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 5043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 14-17 instructions */ 5044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_long: /* 0x9f */ 5049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_long.S */ 5050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide.S */ 5051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 5055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 5056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-long 5062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 5068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 5075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 5076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 5077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__moddi3) # result <- op, a0-a3 changed 5082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 5084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 14-17 instructions */ 5085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_and_long: /* 0xa0 */ 5090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_and_long.S */ 5091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide.S */ 5092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 5096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 5097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-long 5103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 5109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 5117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 5118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, a0, a2 # optional op 5122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a1, a1, a3 # result <- op, a0-a3 changed 5123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 5125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 14-17 instructions */ 5126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_or_long: /* 0xa1 */ 5131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_or_long.S */ 5132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide.S */ 5133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 5137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 5138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-long 5144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 5150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 5158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 5159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a2 # optional op 5163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a1, a1, a3 # result <- op, a0-a3 changed 5164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 5166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 14-17 instructions */ 5167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_xor_long: /* 0xa2 */ 5172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_xor_long.S */ 5173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide.S */ 5174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 5178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 5179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-long 5185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 5191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 5199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 5200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a0, a0, a2 # optional op 5204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a1, a1, a3 # result <- op, a0-a3 changed 5205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 5207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 14-17 instructions */ 5208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shl_long: /* 0xa3 */ 5213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shl_long.S */ 5214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Long integer shift. This is different from the generic 32/64-bit 5216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * binary operations because vAA/vBB are 64-bit but vCC (the shift 5217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6 bits of the shift distance. 5219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* shl-long vAA, vBB, vCC */ 5221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(t2) # t2 <- AA 5223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a3, a0, 255 # a3 <- BB 5224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, a0, 8 # a0 <- CC 5225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vCC 5227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung andi v1, a2, 0x20 # shift< shift & 0x20 5233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll v0, a0, a2 # rlo<- alo << (shift&31) 5234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v1, .Lop_shl_long_finish 5235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not v1, a2 # rhi<- 31-shift (shift is 5b) 5236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, 1 5237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, v1 # alo<- alo >> (32-(shift&31)) 5238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll v1, a1, a2 # rhi<- ahi << (shift&31) 5239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or v1, a0 # rhi<- rhi | alo 5240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- a0/a1 5241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shr_long: /* 0xa4 */ 5245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shr_long.S */ 5246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Long integer shift. This is different from the generic 32/64-bit 5248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * binary operations because vAA/vBB are 64-bit but vCC (the shift 5249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6 bits of the shift distance. 5251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* shr-long vAA, vBB, vCC */ 5253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(t3) # t3 <- AA 5255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a3, a0, 255 # a3 <- BB 5256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, a0, 8 # a0 <- CC 5257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vCC 5259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung andi v0, a2, 0x20 # shift & 0x20 5264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra v1, a1, a2 # rhi<- ahi >> (shift&31) 5265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, .Lop_shr_long_finish 5266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl v0, a0, a2 # rlo<- alo >> (shift&31) 5267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not a0, a2 # alo<- 31-shift (shift is 5b) 5268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, 1 5269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a0 # ahi<- ahi << (32-(shift&31)) 5270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or v0, a1 # rlo<- rlo | ahi 5271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v0 5272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_ushr_long: /* 0xa5 */ 5276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_ushr_long.S */ 5277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Long integer shift. This is different from the generic 32/64-bit 5279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * binary operations because vAA/vBB are 64-bit but vCC (the shift 5280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6 bits of the shift distance. 5282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* ushr-long vAA, vBB, vCC */ 5284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 5286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a3, a0, 255 # a3 <- BB 5287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, a0, 8 # a0 <- CC 5288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a0) # a2 <- vCC 5290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung andi v0, a2, 0x20 # shift & 0x20 5296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl v1, a1, a2 # rhi<- ahi >> (shift&31) 5297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, .Lop_ushr_long_finish 5298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl v0, a0, a2 # rlo<- alo >> (shift&31) 5299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not a0, a2 # alo<- 31-n (shift is 5b) 5300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, 1 5301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a0 # ahi<- ahi << (32-(shift&31)) 5302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or v0, a1 # rlo<- rlo | ahi 5303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 5304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_float: /* 0xa6 */ 5308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_float.S */ 5309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop.S */ 5310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary float operation. 5312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) # a1 <- vCC 5322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a2) # a0 <- vBB 5323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung add.s fv0, fa0, fa1 # f0 = result 5326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 5329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_float: /* 0xa7 */ 5334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_float.S */ 5335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop.S */ 5336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary float operation. 5338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) # a1 <- vCC 5348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a2) # a0 <- vBB 5349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sub.s fv0, fa0, fa1 # f0 = result 5352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 5355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_float: /* 0xa8 */ 5360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_float.S */ 5361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop.S */ 5362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary float operation. 5364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) # a1 <- vCC 5374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a2) # a0 <- vBB 5375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul.s fv0, fa0, fa1 # f0 = result 5378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 5381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_float: /* 0xa9 */ 5386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_float.S */ 5387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop.S */ 5388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary float operation. 5390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) # a1 <- vCC 5400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a2) # a0 <- vBB 5401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div.s fv0, fa0, fa1 # f0 = result 5404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 5407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_float: /* 0xaa */ 5412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_float.S */ 5413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop.S */ 5414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary float operation. 5416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) # a1 <- vCC 5426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, a2) # a0 <- vBB 5427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(fmodf) # f0 = result 5430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- fv0 5431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 5433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_double: /* 0xab */ 5438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_double.S */ 5439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide.S */ 5440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-double, sub-double, mul-double, div-double, 5446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double 5447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a2) 5457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t1) 5458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung add.d fv0, fa0, fa1 5461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 5462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_add_double_finish 5463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_double: /* 0xac */ 5468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_double.S */ 5469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide.S */ 5470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-double, sub-double, mul-double, div-double, 5476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double 5477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a2) 5487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t1) 5488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sub.d fv0, fa0, fa1 5491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 5492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_sub_double_finish 5493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_double: /* 0xad */ 5498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_double.S */ 5499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide.S */ 5500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-double, sub-double, mul-double, div-double, 5506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double 5507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a2) 5517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t1) 5518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul.d fv0, fa0, fa1 5521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 5522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_mul_double_finish 5523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_double: /* 0xae */ 5528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_double.S */ 5529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide.S */ 5530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-double, sub-double, mul-double, div-double, 5536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double 5537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a2) 5547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t1) 5548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div.d fv0, fa0, fa1 5551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 5552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_div_double_finish 5553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_double: /* 0xaf */ 5558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_double.S */ 5559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide.S */ 5560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit binary operation. Provide an "instr" line that 5562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0-a1 op a2-a3". 5563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * for: add-double, sub-double, mul-double, div-double, 5566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double 5567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 5570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 5571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # s5 <- AA 5572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 5573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 5574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, a2) 5577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t1) 5578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(fmod) 5581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 5582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_rem_double_finish 5583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_int_2addr: /* 0xb0 */ 5588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_int_2addr.S */ 5589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 # a0 <- op, a0-a3 changed 5615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_int_2addr: /* 0xb1 */ 5623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_int_2addr.S */ 5624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu a0, a0, a1 # a0 <- op, a0-a3 changed 5650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_int_2addr: /* 0xb2 */ 5658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_int_2addr.S */ 5659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul a0, a0, a1 # a0 <- op, a0-a3 changed 5685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_int_2addr: /* 0xb3 */ 5693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_int_2addr.S */ 5694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 5695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 5714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div a0, a0, a1 # a0 <- op, a0-a3 changed 5721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 5726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 5745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 5751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mflo a0 # a0 <- op, a0-a3 changed 5752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 5757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_int_2addr: /* 0xb4 */ 5761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_int_2addr.S */ 5762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 5763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 5782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mod a0, a0, a1 # a0 <- op, a0-a3 changed 5789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 5794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 5813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 5819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhi a0 # a0 <- op, a0-a3 changed 5820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 5825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_and_int_2addr: /* 0xb5 */ 5829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_and_int_2addr.S */ 5830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, a0, a1 # a0 <- op, a0-a3 changed 5856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_or_int_2addr: /* 0xb6 */ 5864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_or_int_2addr.S */ 5865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a1 # a0 <- op, a0-a3 changed 5891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_xor_int_2addr: /* 0xb7 */ 5899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_xor_int_2addr.S */ 5900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a0, a0, a1 # a0 <- op, a0-a3 changed 5926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shl_int_2addr: /* 0xb8 */ 5934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shl_int_2addr.S */ 5935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, a0, a1 # a0 <- op, a0-a3 changed 5961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 5967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 5968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shr_int_2addr: /* 0xb9 */ 5969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shr_int_2addr.S */ 5970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 5971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 5972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 5974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 5977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 5978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 5979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 5983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 5984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 5985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 5986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 5987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 5988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 5989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 5990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 5991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 5992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 5994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 5995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a0, a0, a1 # a0 <- op, a0-a3 changed 5996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 5997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 5998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 5999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_ushr_int_2addr: /* 0xba */ 6004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_ushr_int_2addr.S */ 6005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binop2addr.S */ 6006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/2addr, shr-int/2addr, ushr-int/2addr 6017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, rOBJ) # a0 <- vA 6022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vB 6023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 6025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, a0, a1 # a0 <- op, a0-a3 changed 6031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_long_2addr: /* 0xbb */ 6039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_long_2addr.S */ 6040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 6041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * See op_add_long.S for details 6042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide2addr.S */ 6044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and-long/2addr, or-long/2addr, xor-long/2addr 6055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double/2addr 6056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 6066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 6067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v0, a2, a0 # optional op 6071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed 6072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-15 instructions */ 6076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_long_2addr: /* 0xbc */ 6081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_long_2addr.S */ 6082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 6083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * See op_sub_long.S for more details 6084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide2addr.S */ 6086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and-long/2addr, or-long/2addr, xor-long/2addr 6097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double/2addr 6098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 6108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 6109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu v0, a0, a2 # optional op 6113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed 6114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-15 instructions */ 6118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_long_2addr: /* 0xbd */ 6123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_long_2addr.S */ 6124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * See op_mul_long.S for more details 6126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* mul-long/2addr vA, vB */ 6128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # vAA.low / high 6132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(t1) # t1 <- B 6134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t1, rFP, t1) # t1 <- &fp[B] 6135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, t1) # vBB.low / high 6136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul v1, a3, a0 # v1= a3a0 6138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 6139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mulu v0, a2, a0 # v0= a2a0 6140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung muhu t1, a2, a0 6141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 6142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung multu a2, a0 6143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhi t1 6144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mflo v0 # v0= a2a0 6145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung #endif 6146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul t2, a2, a1 # t2= a2a1 6147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v1, v1, t1 # v1= a3a0 + hi(a2a0) 6148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu v1, v1, t2 # v1= v1 + a2a1; 6149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t1) # extract opcode from rINST 6152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # vAA <- v0 (low) 6153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, rOBJ) # vAA+1 <- v1 (high) 6154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t1) # jump to next instruction 6155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_long_2addr: /* 0xbe */ 6159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_long_2addr.S */ 6160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide2addr.S */ 6161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and-long/2addr, or-long/2addr, xor-long/2addr 6172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double/2addr 6173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 6182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 6183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 6184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__divdi3) # result <- op, a0-a3 changed 6189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-15 instructions */ 6193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_long_2addr: /* 0xbf */ 6198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_long_2addr.S */ 6199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide2addr.S */ 6200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and-long/2addr, or-long/2addr, xor-long/2addr 6211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double/2addr 6212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 6221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 6222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 6223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__moddi3) # result <- op, a0-a3 changed 6228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, rOBJ) # vAA/vAA+1 <- v0/v1 6230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-15 instructions */ 6232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_and_long_2addr: /* 0xc0 */ 6237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_and_long_2addr.S */ 6238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide2addr.S */ 6239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and-long/2addr, or-long/2addr, xor-long/2addr 6250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double/2addr 6251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 6261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 6262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, a0, a2 # optional op 6266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a1, a1, a3 # result <- op, a0-a3 changed 6267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 6269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-15 instructions */ 6271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_or_long_2addr: /* 0xc1 */ 6276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_or_long_2addr.S */ 6277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide2addr.S */ 6278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and-long/2addr, or-long/2addr, xor-long/2addr 6289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double/2addr 6290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 6300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 6301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a2 # optional op 6305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a1, a1, a3 # result <- op, a0-a3 changed 6306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 6308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-15 instructions */ 6310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_xor_long_2addr: /* 0xc2 */ 6315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_xor_long_2addr.S */ 6316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopWide2addr.S */ 6317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * and-long/2addr, or-long/2addr, xor-long/2addr 6328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-double/2addr 6329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a2, a3, a1) # a2/a3 <- vBB/vBB+1 6336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or t0, a2, a3 # second arg (a2-a3) is zero? 6339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz t0, common_errDivideByZero 6340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a0, a0, a2 # optional op 6344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a1, a1, a3 # result <- op, a0-a3 changed 6345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, rOBJ) # vAA/vAA+1 <- a0/a1 6347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 12-15 instructions */ 6349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shl_long_2addr: /* 0xc3 */ 6354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shl_long_2addr.S */ 6355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 32-bit shift distance. 6358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* shl-long/2addr vA, vB */ 6360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a3) # a2 <- vB 6363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] 6364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t2) # a0/a1 <- vAA/vAA+1 6365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung andi v1, a2, 0x20 # shift< shift & 0x20 6370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll v0, a0, a2 # rlo<- alo << (shift&31) 6371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v1, .Lop_shl_long_2addr_finish 6372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not v1, a2 # rhi<- 31-shift (shift is 5b) 6373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, 1 6374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, v1 # alo<- alo >> (32-(shift&31)) 6375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll v1, a1, a2 # rhi<- ahi << (shift&31) 6376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or v1, a0 # rhi<- rhi | alo 6377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 6378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shr_long_2addr: /* 0xc4 */ 6382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shr_long_2addr.S */ 6383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 32-bit shift distance. 6386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* shr-long/2addr vA, vB */ 6388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t2) # t2 <- A+ 6389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a3) # a2 <- vB 6391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, t2) # t0 <- &fp[A] 6392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung andi v0, a2, 0x20 # shift & 0x20 6397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra v1, a1, a2 # rhi<- ahi >> (shift&31) 6398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, .Lop_shr_long_2addr_finish 6399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl v0, a0, a2 # rlo<- alo >> (shift&31) 6400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not a0, a2 # alo<- 31-shift (shift is 5b) 6401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, 1 6402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a0 # ahi<- ahi << (32-(shift&31)) 6403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or v0, a1 # rlo<- rlo | ahi 6404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- a0/a1 6405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_ushr_long_2addr: /* 0xc5 */ 6409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_ushr_long_2addr.S */ 6410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 32-bit shift distance. 6413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* ushr-long/2addr vA, vB */ 6415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(t3) # t3 <- A+ 6416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a3) # a2 <- vB 6418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, t3) # t0 <- &fp[A] 6419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0/a1 <- vAA/vAA+1 6420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung andi v0, a2, 0x20 # shift & 0x20 6425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl v1, a1, a2 # rhi<- ahi >> (shift&31) 6426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, .Lop_ushr_long_2addr_finish 6427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl v0, a0, a2 # rlo<- alo >> (shift&31) 6428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung not a0, a2 # alo<- 31-n (shift is 5b) 6429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, 1 6430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a0 # ahi<- ahi << (32-(shift&31)) 6431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or v0, a1 # rlo<- rlo | ahi 6432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/vAA+1 <- a0/a1 6433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_float_2addr: /* 0xc6 */ 6437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_float_2addr.S */ 6438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop2addr.S */ 6439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-float/2addr, rem-float/2addr 6446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 6449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, rOBJ) 6451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) 6452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung add.s fv0, fa0, fa1 6455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- result 6456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_float_2addr: /* 0xc7 */ 6463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_float_2addr.S */ 6464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop2addr.S */ 6465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-float/2addr, rem-float/2addr 6472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 6475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, rOBJ) 6477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) 6478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sub.s fv0, fa0, fa1 6481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- result 6482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_float_2addr: /* 0xc8 */ 6489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_float_2addr.S */ 6490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop2addr.S */ 6491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-float/2addr, rem-float/2addr 6498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 6501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, rOBJ) 6503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) 6504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul.s fv0, fa0, fa1 6507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- result 6508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_float_2addr: /* 0xc9 */ 6515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_float_2addr.S */ 6516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop2addr.S */ 6517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-float/2addr, rem-float/2addr 6524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 6527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, rOBJ) 6529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) 6530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div.s fv0, fa0, fa1 6533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- result 6534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_float_2addr: /* 0xca */ 6541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_float_2addr.S */ 6542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinop2addr.S */ 6543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-float/2addr, rem-float/2addr 6550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # t1 <- A+ 6553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 6554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, rOBJ) 6555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) 6556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(fmodf) 6559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_F(fv0, rOBJ) # vAA <- result 6560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_double_2addr: /* 0xcb */ 6567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_double_2addr.S */ 6568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide2addr.S */ 6569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-double/2addr, rem-double/2addr 6576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, t0) 6583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, a1) 6584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung add.d fv0, fa0, fa1 6587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 6588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_sub_double_2addr: /* 0xcc */ 6595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_sub_double_2addr.S */ 6596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide2addr.S */ 6597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-double/2addr, rem-double/2addr 6604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, t0) 6611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, a1) 6612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sub.d fv0, fa0, fa1 6615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 6616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_double_2addr: /* 0xcd */ 6623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_double_2addr.S */ 6624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide2addr.S */ 6625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-double/2addr, rem-double/2addr 6632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, t0) 6639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, a1) 6640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul.d fv0, fa0, fa1 6643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 6644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_double_2addr: /* 0xce */ 6651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_double_2addr.S */ 6652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide2addr.S */ 6653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-double/2addr, rem-double/2addr 6660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, t0) 6667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, a1) 6668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div.d fv0, fa0, fa1 6671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 6672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_double_2addr: /* 0xcf */ 6679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_double_2addr.S */ 6680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/fbinopWide2addr.S */ 6681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 6685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * div-double/2addr, rem-double/2addr 6688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 6690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(rOBJ) # rOBJ <- A+ 6691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 6692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a1, rFP, a1) # a1 <- &fp[B] 6693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa0, fa0f, t0) 6695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, a1) 6696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(fmod) 6699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_F(fv0, fv0f, rOBJ) 6700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 6702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_int_lit16: /* 0xd0 */ 6707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_int_lit16.S */ 6708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 # a0 <- op, a0-a3 changed 6735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rsub_int: /* 0xd1 */ 6743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rsub_int.S */ 6744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu a0, a1, a0 # a0 <- op, a0-a3 changed 6772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_int_lit16: /* 0xd2 */ 6780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_int_lit16.S */ 6781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul a0, a0, a1 # a0 <- op, a0-a3 changed 6808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_int_lit16: /* 0xd3 */ 6816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_int_lit16.S */ 6817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 6818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 6838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div a0, a0, a1 # a0 <- op, a0-a3 changed 6845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 6850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 6870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 6876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mflo a0 # a0 <- op, a0-a3 changed 6877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 6882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_int_lit16: /* 0xd4 */ 6886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_int_lit16.S */ 6887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 6888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 6908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mod a0, a0, a1 # a0 <- op, a0-a3 changed 6915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 6920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 6940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 6946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhi a0 # a0 <- op, a0-a3 changed 6947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 6952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_and_int_lit16: /* 0xd5 */ 6956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_and_int_lit16.S */ 6957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 6965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 6966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 6970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 6971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 6973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 6974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 6975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 6976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 6977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 6978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 6979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 6980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 6983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, a0, a1 # a0 <- op, a0-a3 changed 6984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 6985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 6987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 6989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 6990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 6991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_or_int_lit16: /* 0xd6 */ 6992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_or_int_lit16.S */ 6993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 6994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 6995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 6997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 6998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 6999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 7007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 7010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 7011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 7012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 7014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a1 # a0 <- op, a0-a3 changed 7020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 7023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_xor_int_lit16: /* 0xd7 */ 7028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_xor_int_lit16.S */ 7029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit16.S */ 7030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit16" binary operation. Provide an "instr" line 7032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 7040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 7041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit16 vA, vB, /* +CCCC */ 7043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 7044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- A+ 7046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vB 7047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and rOBJ, rOBJ, 15 7048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # cmp a1, 0; is second operand zero? 7050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a0, a0, a1 # a0 <- op, a0-a3 changed 7056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-13 instructions */ 7059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_add_int_lit8: /* 0xd8 */ 7064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_add_int_lit8.S */ 7065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, a0, a1 # a0 <- op, a0-a3 changed 7093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rsub_int_lit8: /* 0xd9 */ 7101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rsub_int_lit8.S */ 7102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung subu a0, a1, a0 # a0 <- op, a0-a3 changed 7130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_mul_int_lit8: /* 0xda */ 7138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_mul_int_lit8.S */ 7139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mul a0, a0, a1 # a0 <- op, a0-a3 changed 7167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_div_int_lit8: /* 0xdb */ 7175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_div_int_lit8.S */ 7176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 7177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 7198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div a0, a0, a1 # a0 <- op, a0-a3 changed 7205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 7210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 7231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 7237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mflo a0 # a0 <- op, a0-a3 changed 7238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 7243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_rem_int_lit8: /* 0xdc */ 7247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_rem_int_lit8.S */ 7248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 7249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 7270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mod a0, a0, a1 # a0 <- op, a0-a3 changed 7277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 7282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 1 7303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung div zero, a0, a1 # optional op 7309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mfhi a0 # a0 <- op, a0-a3 changed 7310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 7315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_and_int_lit8: /* 0xdd */ 7319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_and_int_lit8.S */ 7320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a0, a0, a1 # a0 <- op, a0-a3 changed 7348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_or_int_lit8: /* 0xde */ 7356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_or_int_lit8.S */ 7357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung or a0, a0, a1 # a0 <- op, a0-a3 changed 7385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_xor_int_lit8: /* 0xdf */ 7393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_xor_int_lit8.S */ 7394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung xor a0, a0, a1 # a0 <- op, a0-a3 changed 7422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shl_int_lit8: /* 0xe0 */ 7430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shl_int_lit8.S */ 7431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a0, a0, a1 # a0 <- op, a0-a3 changed 7459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_shr_int_lit8: /* 0xe1 */ 7467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_shr_int_lit8.S */ 7468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a0, a0, a1 # a0 <- op, a0-a3 changed 7496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_ushr_int_lit8: /* 0xe2 */ 7504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_ushr_int_lit8.S */ 7505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/binopLit8.S */ 7506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * that specifies an instruction that performs "result = a0 op a1". 7509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. (If the result 7510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 7513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. 7514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 7515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # binop/lit8 vAA, vBB, /* +CC */ 7520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 7522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a3, 255 # a2 <- BB 7523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 7524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if 0 7526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 7527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 7528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 7529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # optional op 7532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a0, a0, a1 # a0 <- op, a0-a3 changed 7533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 10-12 instructions */ 7536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_quick: /* 0xe3 */ 7541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_quick.S */ 7542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- object we're operating on 7546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check object for null 7549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_wide_quick: /* 0xe4 */ 7559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_wide_quick.S */ 7560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # iget-wide-quick vA, vB, offset /* CCCC */ 7561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- object we're operating on 7563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check object for null 7566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 # t0 <- a3 + a1 7568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) 7569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(a0, a1, a2) # fp[A] <- a0/a1 7572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_object_quick: /* 0xe5 */ 7577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_object_quick.S */ 7578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iget-object-quick */ 7579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* op vA, vB, offset@CCCC */ 7580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 7583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- object we're operating on 7584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) 7585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 7586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2<- A+ 7587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung PREFETCH_INST(2) # load rINST 7588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez a3, MterpPossibleException # bail out 7589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_OBJECT(v0, a2) # fp[A] <- v0 7590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung ADVANCE(2) # advance rPC 7591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_quick: /* 0xe6 */ 7597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_quick.S */ 7598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iput-quick, iput-object-quick */ 7599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- fp[A] 7606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_wide_quick: /* 0xe7 */ 7615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_wide_quick.S */ 7616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # iput-wide-quick vA, vB, offset /* CCCC */ 7617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a0) # a0 <- A(+) 7618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a1) # a1 <- B 7619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a2, a1) # a2 <- fp[B], the object pointer 7620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check object for null 7621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a2, common_errNullObject # object was null 7622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EAS2(a3, rFP, a0) # a3 <- &fp[A] 7623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(a0, a1, a3) # a0/a1 <- fp[A] 7624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a3, 1) # a3 <- field byte offset 7625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 7627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 7628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_object_quick: /* 0xe8 */ 7634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_object_quick.S */ 7635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iput-object-quick */ 7636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 7638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a0, rFP, OFF_FP_SHADOWFRAME 7639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a1, rPC 7640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 7641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpIputObjectQuick) 7642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 7643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_virtual_quick: /* 0xe9 */ 7650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_virtual_quick.S */ 7651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 7652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 7654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 7656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 7657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeVirtualQuick 7658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 7659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 7660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 7661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 7662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 7663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeVirtualQuick) 7664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 7665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 7666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 7667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 7668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 7669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 7670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_virtual_range_quick: /* 0xea */ 7675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_invoke_virtual_range_quick.S */ 7676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/invoke.S */ 7677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 7678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic invoke handler wrapper. 7679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vB, {vD, vE, vF, vG, vA}, class /* CCCC */ 7681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op {vCCCC..v(CCCC+AA-1)}, meth /* BBBB */ 7682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpInvokeVirtualQuickRange 7683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 7684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 7685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 7686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rPC 7687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a3, rINST 7688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpInvokeVirtualQuickRange) 7689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpException 7690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(3) 7691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 7692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 7693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 7694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 7695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_boolean_quick: /* 0xeb */ 7700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_boolean_quick.S */ 7701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_quick.S */ 7702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iput-quick, iput-object-quick */ 7703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- fp[A] 7710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_byte_quick: /* 0xec */ 7720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_byte_quick.S */ 7721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_quick.S */ 7722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iput-quick, iput-object-quick */ 7723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- fp[A] 7730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_char_quick: /* 0xed */ 7740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_char_quick.S */ 7741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_quick.S */ 7742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iput-quick, iput-object-quick */ 7743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- fp[A] 7750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iput_short_quick: /* 0xee */ 7760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_short_quick.S */ 7761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iput_quick.S */ 7762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iput-quick, iput-object-quick */ 7763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- fp[A] 7770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_boolean_quick: /* 0xef */ 7780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_boolean_quick.S */ 7781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_quick.S */ 7782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- object we're operating on 7786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check object for null 7789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lbu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_byte_quick: /* 0xf0 */ 7800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_byte_quick.S */ 7801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_quick.S */ 7802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- object we're operating on 7806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check object for null 7809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lb a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_char_quick: /* 0xf1 */ 7820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_char_quick.S */ 7821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_quick.S */ 7822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- object we're operating on 7826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check object for null 7829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lhu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_iget_short_quick: /* 0xf2 */ 7840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_short_quick.S */ 7841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_iget_quick.S */ 7842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # op vA, vB, offset /* CCCC */ 7844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a2) # a2 <- B 7845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a3, a2) # a3 <- object we're operating on 7846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a1, 1) # a1 <- field byte offset 7847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA4(a2) # a2 <- A(+) 7848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # check object for null 7849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a3, common_errNullObject # object was null 7850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu t0, a3, a1 7851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lh a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_invoke_lambda: /* 0xf3 */ 7860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Transfer stub to alternate interpreter */ 7861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_f4: /* 0xf4 */ 7866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_f4.S */ 7867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 7868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 7870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_capture_variable: /* 0xf5 */ 7877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Transfer stub to alternate interpreter */ 7878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_create_lambda: /* 0xf6 */ 7883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Transfer stub to alternate interpreter */ 7884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_liberate_variable: /* 0xf7 */ 7889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Transfer stub to alternate interpreter */ 7890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_box_lambda: /* 0xf8 */ 7895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Transfer stub to alternate interpreter */ 7896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unbox_lambda: /* 0xf9 */ 7901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Transfer stub to alternate interpreter */ 7902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_fa: /* 0xfa */ 7907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_fa.S */ 7908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 7909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 7911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_fb: /* 0xfb */ 7918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_fb.S */ 7919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 7920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 7922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_fc: /* 0xfc */ 7929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_fc.S */ 7930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 7931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 7933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_fd: /* 0xfd */ 7940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_fd.S */ 7941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 7942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 7944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_fe: /* 0xfe */ 7951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_fe.S */ 7952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 7953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 7955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 7960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_unused_ff: /* 0xff */ 7962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/op_unused_ff.S */ 7963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/unused.S */ 7964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail to reference interpreter to throw. 7966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpFallback 7968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 7971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 7972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .global artMterpAsmInstructionEnd 7973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungartMterpAsmInstructionEnd: 7974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 7976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * =========================================================================== 7977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Sister implementations 7978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * =========================================================================== 7979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 7980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .global artMterpAsmSisterStart 7981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .type artMterpAsmSisterStart, %function 7982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .text 7983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 4 7984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungartMterpAsmSisterStart: 7985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_packed_switch */ 7987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_packed_switch_finish: 7989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_sparse_switch */ 7993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_sparse_switch_finish: 7995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 7996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 7997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 7998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_cmpl_float */ 7999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpl_float_nan: 8001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 8002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpl_float_finish: 8004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) 8005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 8008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_cmpg_float */ 8010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpg_float_nan: 8012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 8013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpg_float_finish: 8015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) 8016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 8019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_cmpl_double */ 8021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpl_double_nan: 8023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, -1 8024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpl_double_finish: 8026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) 8027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 8030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_cmpg_double */ 8032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpg_double_nan: 8034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rTEMP, 1 8035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_cmpg_double_finish: 8037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) 8038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 8039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 8041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_if_eq */ 8043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_eq_finish: 8045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_if_ne */ 8049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_ne_finish: 8051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_if_lt */ 8055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_lt_finish: 8057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_if_ge */ 8061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_ge_finish: 8063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_if_gt */ 8067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_gt_finish: 8069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_if_le */ 8073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_op_if_le_finish: 8075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_float_to_int */ 8079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Not an entry point as it is used only once !! 8082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungf2i_doconv: 8084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 8085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LFLOAT_TO_INT_max 8086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.s ft2, fa1, fa0 8087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LFLOAT_TO_INT_ret_max 8088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_float_to_int_set_vreg_f 8089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LFLOAT_TO_INT_min 8091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.s ft2, fa0, fa1 8092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LFLOAT_TO_INT_ret_min 8093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_float_to_int_set_vreg_f 8094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.s fa1, fa0 8096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.un.s ft2, fa0, fa1 8097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li.s fv0, 0 8098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_float_to_int_set_vreg_f 8099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 8100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LFLOAT_TO_INT_max 8101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.s fcc0, fa1, fa0 8102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LFLOAT_TO_INT_ret_max 8103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_float_to_int_set_vreg_f 8104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LFLOAT_TO_INT_min 8106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.s fcc0, fa0, fa1 8107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LFLOAT_TO_INT_ret_min 8108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_float_to_int_set_vreg_f 8109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.s fa1, fa0 8111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.un.s fcc0, fa0, fa1 8112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li.s fv0, 0 8113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_float_to_int_set_vreg_f 8114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 8115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung trunc.w.s fv0, fa0 8117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_float_to_int_set_vreg_f 8118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LFLOAT_TO_INT_max: 8120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0x4f000000 8121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LFLOAT_TO_INT_min: 8122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0xcf000000 8123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LFLOAT_TO_INT_ret_max: 8124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0x7fffffff 8125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LFLOAT_TO_INT_ret_min: 8126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0x80000000 8127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_float_to_long */ 8129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungf2l_doconv: 8131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 8132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LLONG_TO_max 8133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.s ft2, fa1, fa0 8134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, ~0 8135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, ~0x80000000 8136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_float_to_long_set_vreg 8137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LLONG_TO_min 8139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.s ft2, fa0, fa1 8140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, 0 8141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, 0x80000000 8142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_float_to_long_set_vreg 8143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.s fa1, fa0 8145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.un.s ft2, fa0, fa1 8146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, 0 8147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, 0 8148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_float_to_long_set_vreg 8149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 8150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LLONG_TO_max 8151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.s fcc0, fa1, fa0 8152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, ~0 8153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, ~0x80000000 8154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_float_to_long_set_vreg 8155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fa1, .LLONG_TO_min 8157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.s fcc0, fa0, fa1 8158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, 0 8159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, 0x80000000 8160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_float_to_long_set_vreg 8161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.s fa1, fa0 8163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.un.s fcc0, fa0, fa1 8164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, 0 8165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, 0 8166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_float_to_long_set_vreg 8167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 8168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__fixsfdi) 8170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_float_to_long_set_vreg 8172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LLONG_TO_max: 8174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0x5f000000 8175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LLONG_TO_min: 8177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0xdf000000 8178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_double_to_int */ 8180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungd2i_doconv: 8182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 8183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_INT_max 8184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.d ft2, fa1, fa0 8186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LDOUBLE_TO_INT_maxret 8187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_double_to_int_set_vreg_f 8188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_INT_min 8190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.d ft2, fa0, fa1 8192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LDOUBLE_TO_INT_minret 8193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_double_to_int_set_vreg_f 8194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.d fa1, fa0 8196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.un.d ft2, fa0, fa1 8197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li.s fv0, 0 8198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_double_to_int_set_vreg_f 8199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 8200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_INT_max 8201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.d fcc0, fa1, fa0 8203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LDOUBLE_TO_INT_maxret 8204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_double_to_int_set_vreg_f 8205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_INT_min 8207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.d fcc0, fa0, fa1 8209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung l.s fv0, .LDOUBLE_TO_INT_minret 8210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_double_to_int_set_vreg_f 8211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.d fa1, fa0 8213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.un.d fcc0, fa0, fa1 8214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li.s fv0, 0 8215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_double_to_int_set_vreg_f 8216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 8217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung trunc.w.d fv0, fa0 8219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_double_to_int_set_vreg_f 8220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_INT_max: 8222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .dword 0x41dfffffffc00000 8223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_INT_min: 8224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .dword 0xc1e0000000000000 # minint, as a double (high word) 8225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_INT_maxret: 8226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0x7fffffff 8227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_INT_minret: 8228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .word 0x80000000 8229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_double_to_long */ 8231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungd2l_doconv: 8233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#ifdef MIPS32REVGE6 8234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_max 8235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.d ft2, fa1, fa0 8237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_ret_max 8238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(rRESULT0, rRESULT1, t0) 8239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_double_to_long_set_vreg 8240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_min 8242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.ule.d ft2, fa0, fa1 8244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_ret_min 8245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(rRESULT0, rRESULT1, t0) 8246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_double_to_long_set_vreg 8247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.d fa1, fa0 8249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung cmp.un.d ft2, fa0, fa1 8250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, 0 8251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, 0 8252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1nez ft2, .Lop_double_to_long_set_vreg 8253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#else 8254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_max 8255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.d fcc0, fa1, fa0 8257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_ret_max 8258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(rRESULT0, rRESULT1, t0) 8259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_double_to_long_set_vreg 8260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_min 8262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64_F(fa1, fa1f, t0) 8263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.ole.d fcc0, fa0, fa1 8264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la t0, .LDOUBLE_TO_LONG_ret_min 8265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung LOAD64(rRESULT0, rRESULT1, t0) 8266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_double_to_long_set_vreg 8267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung mov.d fa1, fa0 8269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung c.un.d fcc0, fa0, fa1 8270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT0, 0 8271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li rRESULT1, 0 8272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bc1t .Lop_double_to_long_set_vreg 8273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 8274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(__fixdfdi) 8275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b .Lop_double_to_long_set_vreg 8276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_LONG_max: 8278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .dword 0x43e0000000000000 # maxlong, as a double (high word) 8279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_LONG_min: 8280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .dword 0xc3e0000000000000 # minlong, as a double (high word) 8281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_LONG_ret_max: 8282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .dword 0x7fffffffffffffff 8283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.LDOUBLE_TO_LONG_ret_min: 8284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .dword 0x8000000000000000 8285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_mul_long */ 8287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_mul_long_finish: 8289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64(v0, v1, a0) # vAA::vAA+1 <- v0(low) :: v1(high) 8291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_shl_long */ 8294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_shl_long_finish: 8296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi 8297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_shr_long */ 8299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_shr_long_finish: 8301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a3, a1, 31 # a3<- sign(ah) 8302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi 8303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_ushr_long */ 8305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_ushr_long_finish: 8307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi 8308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_add_double */ 8310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_add_double_finish: 8312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_sub_double */ 8316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_sub_double_finish: 8318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_mul_double */ 8322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_mul_double_finish: 8324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_div_double */ 8328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_div_double_finish: 8330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_rem_double */ 8334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_rem_double_finish: 8336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 8337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 8338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_shl_long_2addr */ 8340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_shl_long_2addr_finish: 8342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi 8343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_shr_long_2addr */ 8345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_shr_long_2addr_finish: 8347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sra a3, a1, 31 # a3<- sign(ah) 8348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v1, a3, t2, t0) # vAA/vAA+1 <- rlo/rhi 8349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* continuation for op_ushr_long_2addr */ 8351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.Lop_ushr_long_2addr_finish: 8353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG64_GOTO(v1, zero, t3, t0) # vAA/vAA+1 <- rlo/rhi 8354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 8356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .global artMterpAsmSisterEnd 8357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungartMterpAsmSisterEnd: 8358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .global artMterpAsmAltInstructionStart 8361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .type artMterpAsmAltInstructionStart, %function 8362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .text 8363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungartMterpAsmAltInstructionStart = .L_ALT_op_nop 8365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_nop: /* 0x00 */ 8368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (0 * 128) # Addr of primary handler 8377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move: /* 0x01 */ 8386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (1 * 128) # Addr of primary handler 8395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_from16: /* 0x02 */ 8404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (2 * 128) # Addr of primary handler 8413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_16: /* 0x03 */ 8422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (3 * 128) # Addr of primary handler 8431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_wide: /* 0x04 */ 8440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (4 * 128) # Addr of primary handler 8449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_wide_from16: /* 0x05 */ 8458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (5 * 128) # Addr of primary handler 8467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_wide_16: /* 0x06 */ 8476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (6 * 128) # Addr of primary handler 8485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_object: /* 0x07 */ 8494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (7 * 128) # Addr of primary handler 8503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_object_from16: /* 0x08 */ 8512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (8 * 128) # Addr of primary handler 8521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_object_16: /* 0x09 */ 8530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (9 * 128) # Addr of primary handler 8539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_result: /* 0x0a */ 8548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (10 * 128) # Addr of primary handler 8557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_result_wide: /* 0x0b */ 8566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (11 * 128) # Addr of primary handler 8575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_result_object: /* 0x0c */ 8584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (12 * 128) # Addr of primary handler 8593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_move_exception: /* 0x0d */ 8602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (13 * 128) # Addr of primary handler 8611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_return_void: /* 0x0e */ 8620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (14 * 128) # Addr of primary handler 8629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_return: /* 0x0f */ 8638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (15 * 128) # Addr of primary handler 8647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_return_wide: /* 0x10 */ 8656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (16 * 128) # Addr of primary handler 8665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_return_object: /* 0x11 */ 8674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (17 * 128) # Addr of primary handler 8683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_4: /* 0x12 */ 8692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (18 * 128) # Addr of primary handler 8701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_16: /* 0x13 */ 8710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (19 * 128) # Addr of primary handler 8719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const: /* 0x14 */ 8728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (20 * 128) # Addr of primary handler 8737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_high16: /* 0x15 */ 8746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (21 * 128) # Addr of primary handler 8755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_wide_16: /* 0x16 */ 8764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (22 * 128) # Addr of primary handler 8773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_wide_32: /* 0x17 */ 8782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (23 * 128) # Addr of primary handler 8791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_wide: /* 0x18 */ 8800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (24 * 128) # Addr of primary handler 8809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_wide_high16: /* 0x19 */ 8818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (25 * 128) # Addr of primary handler 8827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_string: /* 0x1a */ 8836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (26 * 128) # Addr of primary handler 8845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_string_jumbo: /* 0x1b */ 8854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (27 * 128) # Addr of primary handler 8863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_const_class: /* 0x1c */ 8872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (28 * 128) # Addr of primary handler 8881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_monitor_enter: /* 0x1d */ 8890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (29 * 128) # Addr of primary handler 8899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_monitor_exit: /* 0x1e */ 8908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (30 * 128) # Addr of primary handler 8917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_check_cast: /* 0x1f */ 8926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (31 * 128) # Addr of primary handler 8935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_instance_of: /* 0x20 */ 8944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (32 * 128) # Addr of primary handler 8953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_array_length: /* 0x21 */ 8962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (33 * 128) # Addr of primary handler 8971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_new_instance: /* 0x22 */ 8980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 8982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 8984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 8985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 8986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 8987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 8988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (34 * 128) # Addr of primary handler 8989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 8991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 8993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 8994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 8995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 8996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 8997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_new_array: /* 0x23 */ 8998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 8999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (35 * 128) # Addr of primary handler 9007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_filled_new_array: /* 0x24 */ 9016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (36 * 128) # Addr of primary handler 9025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_filled_new_array_range: /* 0x25 */ 9034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (37 * 128) # Addr of primary handler 9043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_fill_array_data: /* 0x26 */ 9052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (38 * 128) # Addr of primary handler 9061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_throw: /* 0x27 */ 9070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (39 * 128) # Addr of primary handler 9079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_goto: /* 0x28 */ 9088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (40 * 128) # Addr of primary handler 9097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_goto_16: /* 0x29 */ 9106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (41 * 128) # Addr of primary handler 9115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_goto_32: /* 0x2a */ 9124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (42 * 128) # Addr of primary handler 9133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_packed_switch: /* 0x2b */ 9142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (43 * 128) # Addr of primary handler 9151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sparse_switch: /* 0x2c */ 9160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (44 * 128) # Addr of primary handler 9169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_cmpl_float: /* 0x2d */ 9178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (45 * 128) # Addr of primary handler 9187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_cmpg_float: /* 0x2e */ 9196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (46 * 128) # Addr of primary handler 9205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_cmpl_double: /* 0x2f */ 9214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (47 * 128) # Addr of primary handler 9223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_cmpg_double: /* 0x30 */ 9232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (48 * 128) # Addr of primary handler 9241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_cmp_long: /* 0x31 */ 9250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (49 * 128) # Addr of primary handler 9259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_eq: /* 0x32 */ 9268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (50 * 128) # Addr of primary handler 9277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_ne: /* 0x33 */ 9286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (51 * 128) # Addr of primary handler 9295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_lt: /* 0x34 */ 9304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (52 * 128) # Addr of primary handler 9313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_ge: /* 0x35 */ 9322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (53 * 128) # Addr of primary handler 9331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_gt: /* 0x36 */ 9340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (54 * 128) # Addr of primary handler 9349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_le: /* 0x37 */ 9358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (55 * 128) # Addr of primary handler 9367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_eqz: /* 0x38 */ 9376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (56 * 128) # Addr of primary handler 9385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_nez: /* 0x39 */ 9394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (57 * 128) # Addr of primary handler 9403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_ltz: /* 0x3a */ 9412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (58 * 128) # Addr of primary handler 9421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_gez: /* 0x3b */ 9430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (59 * 128) # Addr of primary handler 9439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_gtz: /* 0x3c */ 9448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (60 * 128) # Addr of primary handler 9457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_if_lez: /* 0x3d */ 9466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (61 * 128) # Addr of primary handler 9475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_3e: /* 0x3e */ 9484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (62 * 128) # Addr of primary handler 9493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_3f: /* 0x3f */ 9502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (63 * 128) # Addr of primary handler 9511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_40: /* 0x40 */ 9520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (64 * 128) # Addr of primary handler 9529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_41: /* 0x41 */ 9538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (65 * 128) # Addr of primary handler 9547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_42: /* 0x42 */ 9556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (66 * 128) # Addr of primary handler 9565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_43: /* 0x43 */ 9574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (67 * 128) # Addr of primary handler 9583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aget: /* 0x44 */ 9592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (68 * 128) # Addr of primary handler 9601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aget_wide: /* 0x45 */ 9610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (69 * 128) # Addr of primary handler 9619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aget_object: /* 0x46 */ 9628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (70 * 128) # Addr of primary handler 9637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aget_boolean: /* 0x47 */ 9646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (71 * 128) # Addr of primary handler 9655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aget_byte: /* 0x48 */ 9664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (72 * 128) # Addr of primary handler 9673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aget_char: /* 0x49 */ 9682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (73 * 128) # Addr of primary handler 9691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aget_short: /* 0x4a */ 9700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (74 * 128) # Addr of primary handler 9709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aput: /* 0x4b */ 9718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (75 * 128) # Addr of primary handler 9727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aput_wide: /* 0x4c */ 9736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (76 * 128) # Addr of primary handler 9745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aput_object: /* 0x4d */ 9754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (77 * 128) # Addr of primary handler 9763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aput_boolean: /* 0x4e */ 9772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (78 * 128) # Addr of primary handler 9781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aput_byte: /* 0x4f */ 9790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (79 * 128) # Addr of primary handler 9799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aput_char: /* 0x50 */ 9808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (80 * 128) # Addr of primary handler 9817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_aput_short: /* 0x51 */ 9826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (81 * 128) # Addr of primary handler 9835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget: /* 0x52 */ 9844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (82 * 128) # Addr of primary handler 9853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_wide: /* 0x53 */ 9862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (83 * 128) # Addr of primary handler 9871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_object: /* 0x54 */ 9880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (84 * 128) # Addr of primary handler 9889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_boolean: /* 0x55 */ 9898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (85 * 128) # Addr of primary handler 9907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_byte: /* 0x56 */ 9916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (86 * 128) # Addr of primary handler 9925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_char: /* 0x57 */ 9934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (87 * 128) # Addr of primary handler 9943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_short: /* 0x58 */ 9952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (88 * 128) # Addr of primary handler 9961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput: /* 0x59 */ 9970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (89 * 128) # Addr of primary handler 9979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 9983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 9984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 9985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 9986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 9987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_wide: /* 0x5a */ 9988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 9989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 9990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 9992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 9993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 9995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 9996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (90 * 128) # Addr of primary handler 9997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 9999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_object: /* 0x5b */ 10006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (91 * 128) # Addr of primary handler 10015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_boolean: /* 0x5c */ 10024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (92 * 128) # Addr of primary handler 10033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_byte: /* 0x5d */ 10042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (93 * 128) # Addr of primary handler 10051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_char: /* 0x5e */ 10060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (94 * 128) # Addr of primary handler 10069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_short: /* 0x5f */ 10078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (95 * 128) # Addr of primary handler 10087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sget: /* 0x60 */ 10096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (96 * 128) # Addr of primary handler 10105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sget_wide: /* 0x61 */ 10114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (97 * 128) # Addr of primary handler 10123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sget_object: /* 0x62 */ 10132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (98 * 128) # Addr of primary handler 10141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sget_boolean: /* 0x63 */ 10150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (99 * 128) # Addr of primary handler 10159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sget_byte: /* 0x64 */ 10168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (100 * 128) # Addr of primary handler 10177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sget_char: /* 0x65 */ 10186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (101 * 128) # Addr of primary handler 10195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sget_short: /* 0x66 */ 10204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (102 * 128) # Addr of primary handler 10213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sput: /* 0x67 */ 10222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (103 * 128) # Addr of primary handler 10231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sput_wide: /* 0x68 */ 10240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (104 * 128) # Addr of primary handler 10249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sput_object: /* 0x69 */ 10258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (105 * 128) # Addr of primary handler 10267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sput_boolean: /* 0x6a */ 10276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (106 * 128) # Addr of primary handler 10285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sput_byte: /* 0x6b */ 10294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (107 * 128) # Addr of primary handler 10303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sput_char: /* 0x6c */ 10312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (108 * 128) # Addr of primary handler 10321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sput_short: /* 0x6d */ 10330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (109 * 128) # Addr of primary handler 10339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_virtual: /* 0x6e */ 10348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (110 * 128) # Addr of primary handler 10357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_super: /* 0x6f */ 10366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (111 * 128) # Addr of primary handler 10375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_direct: /* 0x70 */ 10384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (112 * 128) # Addr of primary handler 10393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_static: /* 0x71 */ 10402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (113 * 128) # Addr of primary handler 10411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_interface: /* 0x72 */ 10420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (114 * 128) # Addr of primary handler 10429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_return_void_no_barrier: /* 0x73 */ 10438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (115 * 128) # Addr of primary handler 10447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_virtual_range: /* 0x74 */ 10456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (116 * 128) # Addr of primary handler 10465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_super_range: /* 0x75 */ 10474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (117 * 128) # Addr of primary handler 10483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_direct_range: /* 0x76 */ 10492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (118 * 128) # Addr of primary handler 10501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_static_range: /* 0x77 */ 10510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (119 * 128) # Addr of primary handler 10519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_interface_range: /* 0x78 */ 10528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (120 * 128) # Addr of primary handler 10537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_79: /* 0x79 */ 10546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (121 * 128) # Addr of primary handler 10555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_7a: /* 0x7a */ 10564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (122 * 128) # Addr of primary handler 10573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_neg_int: /* 0x7b */ 10582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (123 * 128) # Addr of primary handler 10591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_not_int: /* 0x7c */ 10600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (124 * 128) # Addr of primary handler 10609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_neg_long: /* 0x7d */ 10618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (125 * 128) # Addr of primary handler 10627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_not_long: /* 0x7e */ 10636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (126 * 128) # Addr of primary handler 10645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_neg_float: /* 0x7f */ 10654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (127 * 128) # Addr of primary handler 10663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_neg_double: /* 0x80 */ 10672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (128 * 128) # Addr of primary handler 10681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_int_to_long: /* 0x81 */ 10690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (129 * 128) # Addr of primary handler 10699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_int_to_float: /* 0x82 */ 10708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (130 * 128) # Addr of primary handler 10717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_int_to_double: /* 0x83 */ 10726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (131 * 128) # Addr of primary handler 10735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_long_to_int: /* 0x84 */ 10744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (132 * 128) # Addr of primary handler 10753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_long_to_float: /* 0x85 */ 10762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (133 * 128) # Addr of primary handler 10771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_long_to_double: /* 0x86 */ 10780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (134 * 128) # Addr of primary handler 10789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_float_to_int: /* 0x87 */ 10798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (135 * 128) # Addr of primary handler 10807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_float_to_long: /* 0x88 */ 10816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (136 * 128) # Addr of primary handler 10825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_float_to_double: /* 0x89 */ 10834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (137 * 128) # Addr of primary handler 10843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_double_to_int: /* 0x8a */ 10852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (138 * 128) # Addr of primary handler 10861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_double_to_long: /* 0x8b */ 10870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (139 * 128) # Addr of primary handler 10879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_double_to_float: /* 0x8c */ 10888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (140 * 128) # Addr of primary handler 10897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_int_to_byte: /* 0x8d */ 10906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (141 * 128) # Addr of primary handler 10915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_int_to_char: /* 0x8e */ 10924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (142 * 128) # Addr of primary handler 10933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_int_to_short: /* 0x8f */ 10942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (143 * 128) # Addr of primary handler 10951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_int: /* 0x90 */ 10960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (144 * 128) # Addr of primary handler 10969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_int: /* 0x91 */ 10978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 10982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 10983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 10984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 10985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 10986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (145 * 128) # Addr of primary handler 10987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 10989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 10991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 10992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 10993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 10994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 10995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_int: /* 0x92 */ 10996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 10997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 10998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (146 * 128) # Addr of primary handler 11005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_int: /* 0x93 */ 11014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (147 * 128) # Addr of primary handler 11023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_int: /* 0x94 */ 11032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (148 * 128) # Addr of primary handler 11041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_and_int: /* 0x95 */ 11050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (149 * 128) # Addr of primary handler 11059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_or_int: /* 0x96 */ 11068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (150 * 128) # Addr of primary handler 11077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_xor_int: /* 0x97 */ 11086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (151 * 128) # Addr of primary handler 11095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shl_int: /* 0x98 */ 11104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (152 * 128) # Addr of primary handler 11113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shr_int: /* 0x99 */ 11122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (153 * 128) # Addr of primary handler 11131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_ushr_int: /* 0x9a */ 11140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (154 * 128) # Addr of primary handler 11149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_long: /* 0x9b */ 11158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (155 * 128) # Addr of primary handler 11167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_long: /* 0x9c */ 11176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (156 * 128) # Addr of primary handler 11185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_long: /* 0x9d */ 11194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (157 * 128) # Addr of primary handler 11203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_long: /* 0x9e */ 11212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (158 * 128) # Addr of primary handler 11221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_long: /* 0x9f */ 11230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (159 * 128) # Addr of primary handler 11239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_and_long: /* 0xa0 */ 11248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (160 * 128) # Addr of primary handler 11257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_or_long: /* 0xa1 */ 11266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (161 * 128) # Addr of primary handler 11275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_xor_long: /* 0xa2 */ 11284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (162 * 128) # Addr of primary handler 11293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shl_long: /* 0xa3 */ 11302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (163 * 128) # Addr of primary handler 11311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shr_long: /* 0xa4 */ 11320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (164 * 128) # Addr of primary handler 11329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_ushr_long: /* 0xa5 */ 11338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (165 * 128) # Addr of primary handler 11347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_float: /* 0xa6 */ 11356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (166 * 128) # Addr of primary handler 11365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_float: /* 0xa7 */ 11374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (167 * 128) # Addr of primary handler 11383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_float: /* 0xa8 */ 11392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (168 * 128) # Addr of primary handler 11401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_float: /* 0xa9 */ 11410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (169 * 128) # Addr of primary handler 11419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_float: /* 0xaa */ 11428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (170 * 128) # Addr of primary handler 11437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_double: /* 0xab */ 11446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (171 * 128) # Addr of primary handler 11455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_double: /* 0xac */ 11464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (172 * 128) # Addr of primary handler 11473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_double: /* 0xad */ 11482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (173 * 128) # Addr of primary handler 11491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_double: /* 0xae */ 11500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (174 * 128) # Addr of primary handler 11509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_double: /* 0xaf */ 11518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (175 * 128) # Addr of primary handler 11527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_int_2addr: /* 0xb0 */ 11536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (176 * 128) # Addr of primary handler 11545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_int_2addr: /* 0xb1 */ 11554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (177 * 128) # Addr of primary handler 11563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_int_2addr: /* 0xb2 */ 11572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (178 * 128) # Addr of primary handler 11581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_int_2addr: /* 0xb3 */ 11590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (179 * 128) # Addr of primary handler 11599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_int_2addr: /* 0xb4 */ 11608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (180 * 128) # Addr of primary handler 11617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_and_int_2addr: /* 0xb5 */ 11626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (181 * 128) # Addr of primary handler 11635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_or_int_2addr: /* 0xb6 */ 11644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (182 * 128) # Addr of primary handler 11653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_xor_int_2addr: /* 0xb7 */ 11662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (183 * 128) # Addr of primary handler 11671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shl_int_2addr: /* 0xb8 */ 11680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (184 * 128) # Addr of primary handler 11689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shr_int_2addr: /* 0xb9 */ 11698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (185 * 128) # Addr of primary handler 11707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_ushr_int_2addr: /* 0xba */ 11716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (186 * 128) # Addr of primary handler 11725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_long_2addr: /* 0xbb */ 11734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (187 * 128) # Addr of primary handler 11743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_long_2addr: /* 0xbc */ 11752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (188 * 128) # Addr of primary handler 11761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_long_2addr: /* 0xbd */ 11770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (189 * 128) # Addr of primary handler 11779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_long_2addr: /* 0xbe */ 11788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (190 * 128) # Addr of primary handler 11797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_long_2addr: /* 0xbf */ 11806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (191 * 128) # Addr of primary handler 11815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_and_long_2addr: /* 0xc0 */ 11824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (192 * 128) # Addr of primary handler 11833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_or_long_2addr: /* 0xc1 */ 11842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (193 * 128) # Addr of primary handler 11851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_xor_long_2addr: /* 0xc2 */ 11860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (194 * 128) # Addr of primary handler 11869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shl_long_2addr: /* 0xc3 */ 11878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (195 * 128) # Addr of primary handler 11887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shr_long_2addr: /* 0xc4 */ 11896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (196 * 128) # Addr of primary handler 11905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 11914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (197 * 128) # Addr of primary handler 11923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_float_2addr: /* 0xc6 */ 11932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (198 * 128) # Addr of primary handler 11941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_float_2addr: /* 0xc7 */ 11950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (199 * 128) # Addr of primary handler 11959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_float_2addr: /* 0xc8 */ 11968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (200 * 128) # Addr of primary handler 11977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 11982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 11983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 11984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 11985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_float_2addr: /* 0xc9 */ 11986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 11987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 11988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 11990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 11991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 11992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 11993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 11994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (201 * 128) # Addr of primary handler 11995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 11997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 11999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_float_2addr: /* 0xca */ 12004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (202 * 128) # Addr of primary handler 12013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_double_2addr: /* 0xcb */ 12022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (203 * 128) # Addr of primary handler 12031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_sub_double_2addr: /* 0xcc */ 12040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (204 * 128) # Addr of primary handler 12049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_double_2addr: /* 0xcd */ 12058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (205 * 128) # Addr of primary handler 12067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_double_2addr: /* 0xce */ 12076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (206 * 128) # Addr of primary handler 12085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_double_2addr: /* 0xcf */ 12094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (207 * 128) # Addr of primary handler 12103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_int_lit16: /* 0xd0 */ 12112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (208 * 128) # Addr of primary handler 12121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rsub_int: /* 0xd1 */ 12130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (209 * 128) # Addr of primary handler 12139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_int_lit16: /* 0xd2 */ 12148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (210 * 128) # Addr of primary handler 12157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12158200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12159200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12160200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12161200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12162200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12163200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12164200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12165200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_int_lit16: /* 0xd3 */ 12166200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12167200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12168200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12169200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12170200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12171200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12172200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12173200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12174200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (211 * 128) # Addr of primary handler 12175200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12176200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12177200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12178200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12179200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12180200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12181200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12182200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12183200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_int_lit16: /* 0xd4 */ 12184200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12185200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12186200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12187200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12188200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12189200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12190200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12191200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12192200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (212 * 128) # Addr of primary handler 12193200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12194200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12195200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12196200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12197200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12198200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12199200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12200200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12201200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_and_int_lit16: /* 0xd5 */ 12202200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12203200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12204200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12205200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12206200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12207200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12208200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12209200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12210200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (213 * 128) # Addr of primary handler 12211200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12212200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12213200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12214200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12215200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12216200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12217200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12218200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12219200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_or_int_lit16: /* 0xd6 */ 12220200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12221200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12222200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12223200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12224200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12225200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12226200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12227200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12228200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (214 * 128) # Addr of primary handler 12229200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12230200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12231200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12232200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12233200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12234200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12235200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12236200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12237200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_xor_int_lit16: /* 0xd7 */ 12238200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12239200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12240200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12241200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12242200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12243200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12244200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12245200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12246200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (215 * 128) # Addr of primary handler 12247200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12248200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12249200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12250200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12251200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12252200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12253200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12254200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12255200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_add_int_lit8: /* 0xd8 */ 12256200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12257200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12258200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12259200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12260200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12261200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12262200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12263200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12264200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (216 * 128) # Addr of primary handler 12265200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12266200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12267200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12268200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12269200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12270200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12271200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12272200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12273200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 12274200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12275200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12276200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12277200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12278200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12279200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12280200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12281200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12282200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (217 * 128) # Addr of primary handler 12283200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12284200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12285200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12286200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12287200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12288200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12289200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12290200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12291200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_mul_int_lit8: /* 0xda */ 12292200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12293200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12294200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12295200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12296200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12297200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12298200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12299200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12300200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (218 * 128) # Addr of primary handler 12301200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12302200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12303200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12304200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12305200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12306200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12307200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12308200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12309200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_div_int_lit8: /* 0xdb */ 12310200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12311200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12312200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12313200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12314200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12315200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12316200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12317200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12318200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (219 * 128) # Addr of primary handler 12319200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12320200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12321200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12322200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12323200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12324200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12325200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12326200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12327200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_rem_int_lit8: /* 0xdc */ 12328200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12329200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12330200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12331200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12332200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12333200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12334200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12335200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12336200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (220 * 128) # Addr of primary handler 12337200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12338200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12339200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12340200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12341200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12342200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12343200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12344200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12345200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_and_int_lit8: /* 0xdd */ 12346200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12347200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12348200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12349200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12350200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12351200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12352200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12353200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12354200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (221 * 128) # Addr of primary handler 12355200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12356200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12357200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12358200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12359200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12360200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12361200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12362200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12363200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_or_int_lit8: /* 0xde */ 12364200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12365200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12366200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12367200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12368200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12369200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12370200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12371200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12372200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (222 * 128) # Addr of primary handler 12373200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12374200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12375200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12376200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12377200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12378200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12379200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12380200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12381200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_xor_int_lit8: /* 0xdf */ 12382200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12383200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12384200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12385200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12386200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12387200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12388200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12389200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12390200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (223 * 128) # Addr of primary handler 12391200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12392200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12393200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12394200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12395200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12396200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12397200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12398200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12399200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shl_int_lit8: /* 0xe0 */ 12400200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12401200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12402200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12403200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12404200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12405200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12406200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12407200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12408200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (224 * 128) # Addr of primary handler 12409200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12410200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12411200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12412200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12413200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12414200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12415200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12416200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12417200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_shr_int_lit8: /* 0xe1 */ 12418200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12419200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12420200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12421200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12422200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12423200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12424200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12425200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12426200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (225 * 128) # Addr of primary handler 12427200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12428200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12429200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12430200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12431200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12432200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12433200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12434200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12435200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 12436200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12437200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12438200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12439200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12440200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12441200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12442200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12443200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12444200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (226 * 128) # Addr of primary handler 12445200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12446200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12447200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12448200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12449200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12450200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12451200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12452200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12453200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_quick: /* 0xe3 */ 12454200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12455200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12456200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12457200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12458200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12459200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12460200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12461200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12462200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (227 * 128) # Addr of primary handler 12463200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12464200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12465200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12466200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12467200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12468200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12469200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12470200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12471200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_wide_quick: /* 0xe4 */ 12472200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12473200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12474200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12475200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12476200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12477200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12478200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12479200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12480200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (228 * 128) # Addr of primary handler 12481200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12482200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12483200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12484200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12485200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12486200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12487200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12488200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12489200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_object_quick: /* 0xe5 */ 12490200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12491200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12492200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12493200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12494200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12495200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12496200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12497200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12498200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (229 * 128) # Addr of primary handler 12499200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12500200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12501200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12502200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12503200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12504200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12505200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12506200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12507200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_quick: /* 0xe6 */ 12508200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12509200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12510200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12511200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12512200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12513200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12514200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12515200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12516200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (230 * 128) # Addr of primary handler 12517200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12518200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12519200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12520200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12521200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12522200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12523200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12524200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12525200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_wide_quick: /* 0xe7 */ 12526200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12527200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12528200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12529200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12530200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12531200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12532200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12533200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12534200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (231 * 128) # Addr of primary handler 12535200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12536200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12537200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12538200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12539200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12540200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12541200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12542200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12543200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_object_quick: /* 0xe8 */ 12544200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12545200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12546200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12547200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12548200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12549200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12550200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12551200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12552200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (232 * 128) # Addr of primary handler 12553200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12554200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12555200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12556200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12557200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12558200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12559200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12560200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12561200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 12562200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12563200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12564200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12565200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12566200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12567200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12568200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12569200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12570200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (233 * 128) # Addr of primary handler 12571200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12572200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12573200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12574200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12575200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12576200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12577200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12578200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12579200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 12580200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12581200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12582200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12583200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12584200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12585200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12586200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12587200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12588200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (234 * 128) # Addr of primary handler 12589200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12590200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12591200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12592200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12593200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12594200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12595200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12596200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12597200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_boolean_quick: /* 0xeb */ 12598200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12599200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12600200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12601200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12602200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12603200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12604200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12605200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12606200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (235 * 128) # Addr of primary handler 12607200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12608200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12609200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12610200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12611200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12612200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12613200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12614200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12615200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_byte_quick: /* 0xec */ 12616200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12617200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12618200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12619200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12620200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12621200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12622200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12623200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12624200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (236 * 128) # Addr of primary handler 12625200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12626200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12627200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12628200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12629200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12630200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12631200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12632200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12633200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_char_quick: /* 0xed */ 12634200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12635200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12636200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12637200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12638200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12639200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12640200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12641200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12642200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (237 * 128) # Addr of primary handler 12643200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12644200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12645200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12646200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12647200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12648200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12649200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12650200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12651200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iput_short_quick: /* 0xee */ 12652200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12653200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12654200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12655200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12656200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12657200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12658200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12659200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12660200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (238 * 128) # Addr of primary handler 12661200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12662200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12663200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12664200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12665200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12666200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12667200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12668200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12669200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_boolean_quick: /* 0xef */ 12670200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12671200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12672200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12673200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12674200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12675200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12676200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12677200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12678200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (239 * 128) # Addr of primary handler 12679200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12680200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12681200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12682200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12683200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12684200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12685200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12686200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12687200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_byte_quick: /* 0xf0 */ 12688200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12689200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12690200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12691200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12692200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12693200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12694200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12695200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12696200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (240 * 128) # Addr of primary handler 12697200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12698200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12699200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12700200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12701200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12702200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12703200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12704200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12705200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_char_quick: /* 0xf1 */ 12706200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12707200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12708200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12709200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12710200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12711200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12712200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12713200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12714200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (241 * 128) # Addr of primary handler 12715200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12716200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12717200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12718200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12719200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12720200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12721200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12722200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12723200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_iget_short_quick: /* 0xf2 */ 12724200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12725200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12726200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12727200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12728200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12729200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12730200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12731200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12732200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (242 * 128) # Addr of primary handler 12733200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12734200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12735200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12736200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12737200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12738200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12739200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12740200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12741200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_invoke_lambda: /* 0xf3 */ 12742200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12743200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12744200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12745200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12746200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12747200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12748200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12749200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12750200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (243 * 128) # Addr of primary handler 12751200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12752200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12753200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12754200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12755200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12756200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12757200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12758200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12759200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_f4: /* 0xf4 */ 12760200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12761200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12762200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12763200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12764200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12765200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12766200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12767200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12768200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (244 * 128) # Addr of primary handler 12769200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12770200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12771200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12772200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12773200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12774200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12775200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12776200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12777200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_capture_variable: /* 0xf5 */ 12778200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12779200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12780200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12781200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12782200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12783200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12784200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12785200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12786200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (245 * 128) # Addr of primary handler 12787200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12788200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12789200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12790200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12791200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12792200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12793200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12794200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12795200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_create_lambda: /* 0xf6 */ 12796200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12797200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12798200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12799200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12800200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12801200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12802200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12803200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12804200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (246 * 128) # Addr of primary handler 12805200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12806200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12807200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12808200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12809200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12810200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12811200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12812200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12813200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_liberate_variable: /* 0xf7 */ 12814200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12815200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12816200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12817200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12818200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12819200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12820200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12821200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12822200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (247 * 128) # Addr of primary handler 12823200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12824200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12825200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12826200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12827200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12828200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12829200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12830200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12831200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_box_lambda: /* 0xf8 */ 12832200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12833200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12834200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12835200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12836200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12837200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12838200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12839200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12840200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (248 * 128) # Addr of primary handler 12841200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12842200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12843200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12844200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12845200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12846200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12847200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12848200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12849200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unbox_lambda: /* 0xf9 */ 12850200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12851200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12852200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12853200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12854200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12855200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12856200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12857200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12858200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (249 * 128) # Addr of primary handler 12859200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12860200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12861200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12862200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12863200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12864200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12865200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12866200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12867200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_fa: /* 0xfa */ 12868200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12869200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12870200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12871200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12872200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12873200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12874200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12875200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12876200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (250 * 128) # Addr of primary handler 12877200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12878200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12879200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12880200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12881200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12882200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12883200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12884200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12885200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_fb: /* 0xfb */ 12886200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12887200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12888200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12889200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12890200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12891200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12892200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12893200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12894200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (251 * 128) # Addr of primary handler 12895200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12896200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12897200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12898200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12899200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12900200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12901200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12902200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12903200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_fc: /* 0xfc */ 12904200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12905200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12906200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12907200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12908200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12909200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12910200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12911200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12912200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (252 * 128) # Addr of primary handler 12913200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12914200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12915200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12916200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12917200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12918200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12919200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12920200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12921200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_fd: /* 0xfd */ 12922200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12923200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12924200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12925200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12926200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12927200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12928200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12929200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12930200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (253 * 128) # Addr of primary handler 12931200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12932200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12933200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12934200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12935200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12936200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12937200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12938200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12939200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_fe: /* 0xfe */ 12940200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12941200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12942200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12943200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12944200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12945200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12946200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12947200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12948200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (254 * 128) # Addr of primary handler 12949200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12950200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12951200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12952200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12953200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12954200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12955200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* ------------------------------ */ 12956200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12957200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung.L_ALT_op_unused_ff: /* 0xff */ 12958200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/alt_stub.S */ 12959200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12960200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12961200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * any interesting requests and then jump to the real instruction 12962200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * handler. Note that the call to MterpCheckBefore is done as a tail call. 12963200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12964200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .extern MterpCheckBefore 12965200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12966200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la ra, artMterpAsmInstructionStart + (255 * 128) # Addr of primary handler 12967200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12968200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF # arg0 12969200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12970200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung la a2, MterpCheckBefore 12971200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, a2 # Tail call to Mterp(self, shadow_frame) 12972200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12973200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .balign 128 12974200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 12975200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .global artMterpAsmAltInstructionEnd 12976200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungartMterpAsmAltInstructionEnd: 12977200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* File: mips/footer.S */ 12978200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12979200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * =========================================================================== 12980200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Common subroutines and data 12981200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * =========================================================================== 12982200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12983200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12984200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .text 12985200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .align 2 12986200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 12987200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 12988200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * We've detected a condition that will result in an exception, but the exception 12989200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 12990200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * TUNING: for consistency, we may want to just go ahead and handle these here. 12991200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 12992200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungcommon_errDivideByZero: 12993200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 12994200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 12995200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 12996200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 12997200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogDivideByZeroException) 12998200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 12999200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCommonFallback 13000200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13001200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungcommon_errArrayIndex: 13002200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13003200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13004200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13005200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13006200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogArrayIndexException) 13007200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13008200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCommonFallback 13009200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13010200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungcommon_errNegativeArraySize: 13011200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13012200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13013200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13014200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13015200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogNegativeArraySizeException) 13016200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13017200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCommonFallback 13018200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13019200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungcommon_errNoSuchMethod: 13020200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13021200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13022200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13023200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13024200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogNoSuchMethodException) 13025200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13026200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCommonFallback 13027200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13028200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungcommon_errNullObject: 13029200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13030200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13031200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13032200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13033200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogNullObjectException) 13034200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13035200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCommonFallback 13036200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13037200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leungcommon_exceptionThrown: 13038200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13039200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13040200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13041200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13042200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogExceptionThrownException) 13043200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13044200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCommonFallback 13045200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13046200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpSuspendFallback: 13047200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13048200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13049200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13050200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13051200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, THREAD_FLAGS_OFFSET(rSELF) 13052200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogSuspendFallback) 13053200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13054200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpCommonFallback 13055200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13056200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 13057200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If we're here, something is out of the ordinary. If there is a pending 13058200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * exception, handle it. Otherwise, roll back and retry with the reference 13059200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * interpreter. 13060200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 13061200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpPossibleException: 13062200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, THREAD_EXCEPTION_OFFSET(rSELF) 13063200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a0, MterpFallback # If exception, fall back to reference interpreter. 13064200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* intentional fallthrough - handle pending exception. */ 13065200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 13066200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * On return from a runtime helper routine, we've found a pending exception. 13067200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Can we handle it here - or need to bail out to caller? 13068200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 13069200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 13070200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpException: 13071200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13072200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13073200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpHandleException) # (self, shadow_frame) 13074200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz v0, MterpExceptionReturn # no local catch, back to caller. 13075200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a0, OFF_FP_CODE_ITEM(rFP) 13076200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a1, OFF_FP_DEX_PC(rFP) 13077200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 13078200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rPC, a0, CODEITEM_INSNS_OFFSET 13079200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sll a1, a1, 1 13080200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu rPC, rPC, a1 # generate new dex_pc_ptr 13081200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* Do we need to switch interpreters? */ 13082200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpShouldSwitchInterpreters) 13083200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 13084200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* resume execution at catch block */ 13085200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13086200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_INST() 13087200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) 13088200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) 13089200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* NOTE: no fallthrough */ 13090200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13091200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 13092200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Check for suspend check request. Assumes rINST already loaded, rPC advanced and 13093200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * still needs to get the opcode and branch to it, and flags are in lr. 13094200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 13095200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpCheckSuspendAndContinue: 13096200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh rIBASE 13097200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 13098200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez ra, 1f 13099200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 13100200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 13101200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung1: 13102200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13103200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13104200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpSuspendCheck) # (self) 13105200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung bnez v0, MterpFallback 13106200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 13107200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GOTO_OPCODE(t0) # jump to next instruction 13108200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13109200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 13110200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * On-stack replacement has happened, and now we've returned from the compiled method. 13111200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 13112200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpOnStackReplacement: 13113200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13114200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13115200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13116200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a2, rINST 13117200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogOSR) 13118200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13119200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li v0, 1 # Signal normal return 13120200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpDone 13121200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13122200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 13123200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Bail out to reference interpreter. 13124200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 13125200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpFallback: 13126200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung EXPORT_PC() 13127200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#if MTERP_LOGGING 13128200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move a0, rSELF 13129200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung addu a1, rFP, OFF_FP_SHADOWFRAME 13130200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung JAL(MterpLogFallback) 13131200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung#endif 13132200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpCommonFallback: 13133200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung move v0, zero # signal retry with reference interpreter. 13134200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpDone 13135200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* 13136200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * We pushed some registers on the stack in ExecuteMterpImpl, then saved 13137200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * SP and LR. Here we restore SP, restore the registers, and then restore 13138200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * LR to PC. 13139200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 13140200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * On entry: 13141200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * uint32_t* rFP (should still be live, pointer to base of vregs) 13142200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 13143200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpExceptionReturn: 13144200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li v0, 1 # signal return to caller. 13145200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung b MterpDone 13146200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpReturn: 13147200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung lw a2, OFF_FP_RESULT_REGISTER(rFP) 13148200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw v0, 0(a2) 13149200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung sw v1, 4(a2) 13150200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung li v0, 1 # signal return to caller. 13151200f040af3e4fe9e178cb63c90860d58d90ef665Douglas LeungMterpDone: 13152200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung/* Restore from the stack and return. Frame size = STACK_SIZE */ 13153200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung STACK_LOAD_FULL() 13154200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung jalr zero, ra 13155200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13156200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .end ExecuteMterpImpl 13157200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 13158