1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
16
17
18#include "ARMFrameLowering.h"
19#include "ARMISelLowering.h"
20#include "ARMInstrInfo.h"
21#include "ARMSelectionDAGInfo.h"
22#include "ARMSubtarget.h"
23#include "MCTargetDesc/ARMMCTargetDesc.h"
24#include "Thumb1FrameLowering.h"
25#include "Thumb1InstrInfo.h"
26#include "Thumb2InstrInfo.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/MC/MCInstrItineraries.h"
30#include "llvm/Target/TargetSubtargetInfo.h"
31#include <string>
32
33#define GET_SUBTARGETINFO_HEADER
34#include "ARMGenSubtargetInfo.inc"
35
36namespace llvm {
37class GlobalValue;
38class StringRef;
39class TargetOptions;
40class ARMBaseTargetMachine;
41
42class ARMSubtarget : public ARMGenSubtargetInfo {
43protected:
44  enum ARMProcFamilyEnum {
45    Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
46    CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexA35, CortexA53,
47    CortexA57, CortexA72, Krait, Swift
48  };
49  enum ARMProcClassEnum {
50    None, AClass, RClass, MClass
51  };
52  enum ARMArchEnum {
53    ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
54    ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
55    ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a
56  };
57
58  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
59  ARMProcFamilyEnum ARMProcFamily;
60
61  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
62  ARMProcClassEnum ARMProcClass;
63
64  /// ARMArch - ARM architecture
65  ARMArchEnum ARMArch;
66
67  /// HasV4TOps, HasV5TOps, HasV5TEOps,
68  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
69  /// Specify whether target support specific ARM ISA variants.
70  bool HasV4TOps;
71  bool HasV5TOps;
72  bool HasV5TEOps;
73  bool HasV6Ops;
74  bool HasV6MOps;
75  bool HasV6KOps;
76  bool HasV6T2Ops;
77  bool HasV7Ops;
78  bool HasV8Ops;
79  bool HasV8_1aOps;
80  bool HasV8_2aOps;
81
82  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
83  /// floating point ISAs are supported.
84  bool HasVFPv2;
85  bool HasVFPv3;
86  bool HasVFPv4;
87  bool HasFPARMv8;
88  bool HasNEON;
89
90  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
91  /// specified. Use the method useNEONForSinglePrecisionFP() to
92  /// determine if NEON should actually be used.
93  bool UseNEONForSinglePrecisionFP;
94
95  /// UseMulOps - True if non-microcoded fused integer multiply-add and
96  /// multiply-subtract instructions should be used.
97  bool UseMulOps;
98
99  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
100  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
101  bool SlowFPVMLx;
102
103  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
104  /// forwarding to allow mul + mla being issued back to back.
105  bool HasVMLxForwarding;
106
107  /// SlowFPBrcc - True if floating point compare + branch is slow.
108  bool SlowFPBrcc;
109
110  /// InThumbMode - True if compiling for Thumb, false for ARM.
111  bool InThumbMode;
112
113  /// UseSoftFloat - True if we're using software floating point features.
114  bool UseSoftFloat;
115
116  /// HasThumb2 - True if Thumb2 instructions are supported.
117  bool HasThumb2;
118
119  /// NoARM - True if subtarget does not support ARM mode execution.
120  bool NoARM;
121
122  /// ReserveR9 - True if R9 is not available as a general purpose register.
123  bool ReserveR9;
124
125  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
126  /// 32-bit imms (including global addresses).
127  bool NoMovt;
128
129  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
130  /// must be able to synthesize call stubs for interworking between ARM and
131  /// Thumb.
132  bool SupportsTailCall;
133
134  /// HasFP16 - True if subtarget supports half-precision FP conversions
135  bool HasFP16;
136
137  /// HasFullFP16 - True if subtarget supports half-precision FP operations
138  bool HasFullFP16;
139
140  /// HasD16 - True if subtarget is limited to 16 double precision
141  /// FP registers for VFPv3.
142  bool HasD16;
143
144  /// HasHardwareDivide - True if subtarget supports [su]div
145  bool HasHardwareDivide;
146
147  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
148  bool HasHardwareDivideInARM;
149
150  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
151  /// instructions.
152  bool HasT2ExtractPack;
153
154  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
155  /// instructions.
156  bool HasDataBarrier;
157
158  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
159  /// over 16-bit ones.
160  bool Pref32BitThumb;
161
162  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
163  /// that partially update CPSR and add false dependency on the previous
164  /// CPSR setting instruction.
165  bool AvoidCPSRPartialUpdate;
166
167  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
168  /// movs with shifter operand (i.e. asr, lsl, lsr).
169  bool AvoidMOVsShifterOperand;
170
171  /// HasRAS - Some processors perform return stack prediction. CodeGen should
172  /// avoid issue "normal" call instructions to callees which do not return.
173  bool HasRAS;
174
175  /// HasMPExtension - True if the subtarget supports Multiprocessing
176  /// extension (ARMv7 only).
177  bool HasMPExtension;
178
179  /// HasVirtualization - True if the subtarget supports the Virtualization
180  /// extension.
181  bool HasVirtualization;
182
183  /// FPOnlySP - If true, the floating point unit only supports single
184  /// precision.
185  bool FPOnlySP;
186
187  /// If true, the processor supports the Performance Monitor Extensions. These
188  /// include a generic cycle-counter as well as more fine-grained (often
189  /// implementation-specific) events.
190  bool HasPerfMon;
191
192  /// HasTrustZone - if true, processor supports TrustZone security extensions
193  bool HasTrustZone;
194
195  /// HasCrypto - if true, processor supports Cryptography extensions
196  bool HasCrypto;
197
198  /// HasCRC - if true, processor supports CRC instructions
199  bool HasCRC;
200
201  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
202  /// particularly effective at zeroing a VFP register.
203  bool HasZeroCycleZeroing;
204
205  /// StrictAlign - If true, the subtarget disallows unaligned memory
206  /// accesses for some types.  For details, see
207  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
208  bool StrictAlign;
209
210  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
211  ///  blocks to conform to ARMv8 rule.
212  bool RestrictIT;
213
214  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
215  /// and such) instructions.
216  bool HasDSP;
217
218  /// NaCl TRAP instruction is generated instead of the regular TRAP.
219  bool UseNaClTrap;
220
221  /// Force long to be a 64-bit type (RenderScript-specific)
222  bool UseLong64;
223
224  /// Generate calls via indirect call instructions.
225  bool GenLongCalls;
226
227  /// Target machine allowed unsafe FP math (such as use of NEON fp)
228  bool UnsafeFPMath;
229
230  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
231  bool UseSjLjEH;
232
233  /// stackAlignment - The minimum alignment known to hold of the stack frame on
234  /// entry to the function and which must be maintained by every function.
235  unsigned stackAlignment;
236
237  /// CPUString - String name of used CPU.
238  std::string CPUString;
239
240  /// IsLittle - The target is Little Endian
241  bool IsLittle;
242
243  /// TargetTriple - What processor and OS we're targeting.
244  Triple TargetTriple;
245
246  /// SchedModel - Processor specific instruction costs.
247  MCSchedModel SchedModel;
248
249  /// Selected instruction itineraries (one entry per itinerary class.)
250  InstrItineraryData InstrItins;
251
252  /// Options passed via command line that could influence the target
253  const TargetOptions &Options;
254
255  const ARMBaseTargetMachine &TM;
256
257public:
258  /// This constructor initializes the data members to match that
259  /// of the specified triple.
260  ///
261  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
262               const ARMBaseTargetMachine &TM, bool IsLittle);
263
264  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
265  /// that still makes it profitable to inline the call.
266  unsigned getMaxInlineSizeThreshold() const {
267    return 64;
268  }
269  /// ParseSubtargetFeatures - Parses features string setting specified
270  /// subtarget options.  Definition of function is auto generated by tblgen.
271  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
272
273  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
274  /// so that we can use initializer lists for subtarget initialization.
275  ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
276
277  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
278    return &TSInfo;
279  }
280  const ARMBaseInstrInfo *getInstrInfo() const override {
281    return InstrInfo.get();
282  }
283  const ARMTargetLowering *getTargetLowering() const override {
284    return &TLInfo;
285  }
286  const ARMFrameLowering *getFrameLowering() const override {
287    return FrameLowering.get();
288  }
289  const ARMBaseRegisterInfo *getRegisterInfo() const override {
290    return &InstrInfo->getRegisterInfo();
291  }
292
293private:
294  ARMSelectionDAGInfo TSInfo;
295  // Either Thumb1FrameLowering or ARMFrameLowering.
296  std::unique_ptr<ARMFrameLowering> FrameLowering;
297  // Either Thumb1InstrInfo or Thumb2InstrInfo.
298  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
299  ARMTargetLowering   TLInfo;
300
301  void initializeEnvironment();
302  void initSubtargetFeatures(StringRef CPU, StringRef FS);
303  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
304
305public:
306  void computeIssueWidth();
307
308  bool hasV4TOps()  const { return HasV4TOps;  }
309  bool hasV5TOps()  const { return HasV5TOps;  }
310  bool hasV5TEOps() const { return HasV5TEOps; }
311  bool hasV6Ops()   const { return HasV6Ops;   }
312  bool hasV6MOps()  const { return HasV6MOps;  }
313  bool hasV6KOps()  const { return HasV6KOps; }
314  bool hasV6T2Ops() const { return HasV6T2Ops; }
315  bool hasV7Ops()   const { return HasV7Ops;  }
316  bool hasV8Ops()   const { return HasV8Ops;  }
317  bool hasV8_1aOps() const { return HasV8_1aOps; }
318  bool hasV8_2aOps() const { return HasV8_2aOps; }
319
320  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
321  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
322  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
323  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
324  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
325  bool isSwift()    const { return ARMProcFamily == Swift; }
326  bool isCortexM3() const { return CPUString == "cortex-m3"; }
327  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
328  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
329  bool isKrait() const { return ARMProcFamily == Krait; }
330
331  bool hasARMOps() const { return !NoARM; }
332
333  bool hasVFP2() const { return HasVFPv2; }
334  bool hasVFP3() const { return HasVFPv3; }
335  bool hasVFP4() const { return HasVFPv4; }
336  bool hasFPARMv8() const { return HasFPARMv8; }
337  bool hasNEON() const { return HasNEON;  }
338  bool hasCrypto() const { return HasCrypto; }
339  bool hasCRC() const { return HasCRC; }
340  bool hasVirtualization() const { return HasVirtualization; }
341  bool useNEONForSinglePrecisionFP() const {
342    return hasNEON() && UseNEONForSinglePrecisionFP;
343  }
344
345  bool hasDivide() const { return HasHardwareDivide; }
346  bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
347  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
348  bool hasDataBarrier() const { return HasDataBarrier; }
349  bool hasAnyDataBarrier() const {
350    return HasDataBarrier || (hasV6Ops() && !isThumb());
351  }
352  bool useMulOps() const { return UseMulOps; }
353  bool useFPVMLx() const { return !SlowFPVMLx; }
354  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
355  bool isFPBrccSlow() const { return SlowFPBrcc; }
356  bool isFPOnlySP() const { return FPOnlySP; }
357  bool hasPerfMon() const { return HasPerfMon; }
358  bool hasTrustZone() const { return HasTrustZone; }
359  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
360  bool prefers32BitThumb() const { return Pref32BitThumb; }
361  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
362  bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
363  bool hasRAS() const { return HasRAS; }
364  bool hasMPExtension() const { return HasMPExtension; }
365  bool hasDSP() const { return HasDSP; }
366  bool useNaClTrap() const { return UseNaClTrap; }
367  bool useSjLjEH() const { return UseSjLjEH; }
368  bool genLongCalls() const { return GenLongCalls; }
369
370  bool hasFP16() const { return HasFP16; }
371  bool hasD16() const { return HasD16; }
372  bool hasFullFP16() const { return HasFullFP16; }
373
374  const Triple &getTargetTriple() const { return TargetTriple; }
375
376  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
377  bool isTargetIOS() const { return TargetTriple.isiOS(); }
378  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
379  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
380  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
381  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
382  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
383
384  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
385  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
386  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
387
388  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
389  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
390  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
391  // even for GNUEABI, so we can make a distinction here and still conform to
392  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
393  // FIXME: The Darwin exception is temporary, while we move users to
394  // "*-*-*-macho" triples as quickly as possible.
395  bool isTargetAEABI() const {
396    return (TargetTriple.getEnvironment() == Triple::EABI ||
397            TargetTriple.getEnvironment() == Triple::EABIHF) &&
398           !isTargetDarwin() && !isTargetWindows();
399  }
400  bool isTargetGNUAEABI() const {
401    return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
402            TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
403           !isTargetDarwin() && !isTargetWindows();
404  }
405
406  // ARM Targets that support EHABI exception handling standard
407  // Darwin uses SjLj. Other targets might need more checks.
408  bool isTargetEHABICompatible() const {
409    return (TargetTriple.getEnvironment() == Triple::EABI ||
410            TargetTriple.getEnvironment() == Triple::GNUEABI ||
411            TargetTriple.getEnvironment() == Triple::EABIHF ||
412            TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
413            isTargetAndroid()) &&
414           !isTargetDarwin() && !isTargetWindows();
415  }
416
417  bool isTargetHardFloat() const {
418    // FIXME: this is invalid for WindowsCE
419    return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
420           TargetTriple.getEnvironment() == Triple::EABIHF ||
421           isTargetWindows() || isAAPCS16_ABI();
422  }
423  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
424
425  bool isAPCS_ABI() const;
426  bool isAAPCS_ABI() const;
427  bool isAAPCS16_ABI() const;
428
429  bool useSoftFloat() const { return UseSoftFloat; }
430  bool isThumb() const { return InThumbMode; }
431  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
432  bool isThumb2() const { return InThumbMode && HasThumb2; }
433  bool hasThumb2() const { return HasThumb2; }
434  bool isMClass() const { return ARMProcClass == MClass; }
435  bool isRClass() const { return ARMProcClass == RClass; }
436  bool isAClass() const { return ARMProcClass == AClass; }
437
438  bool isR9Reserved() const {
439    return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
440  }
441
442  bool useStride4VFPs(const MachineFunction &MF) const;
443
444  bool useMovt(const MachineFunction &MF) const;
445
446  bool supportsTailCall() const { return SupportsTailCall; }
447
448  bool allowsUnalignedMem() const { return !StrictAlign; }
449
450  bool restrictIT() const { return RestrictIT; }
451
452  const std::string & getCPUString() const { return CPUString; }
453
454  bool isLittle() const { return IsLittle; }
455
456  unsigned getMispredictionPenalty() const;
457
458  /// This function returns true if the target has sincos() routine in its
459  /// compiler runtime or math libraries.
460  bool hasSinCos() const;
461
462  /// Returns true if machine scheduler should be enabled.
463  bool enableMachineScheduler() const override;
464
465  /// True for some subtargets at > -O0.
466  bool enablePostRAScheduler() const override;
467
468  // enableAtomicExpand- True if we need to expand our atomics.
469  bool enableAtomicExpand() const override;
470
471  /// getInstrItins - Return the instruction itineraries based on subtarget
472  /// selection.
473  const InstrItineraryData *getInstrItineraryData() const override {
474    return &InstrItins;
475  }
476
477  /// getStackAlignment - Returns the minimum alignment known to hold of the
478  /// stack frame on entry to the function and which must be maintained by every
479  /// function for this subtarget.
480  unsigned getStackAlignment() const { return stackAlignment; }
481
482  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
483  /// symbol.
484  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
485
486  /// True if fast-isel is used.
487  bool useFastISel() const;
488};
489} // End llvm namespace
490
491#endif  // ARMSUBTARGET_H
492