ARMInstPrinter.cpp revision 01208d56e8341c17bb7dbeaf6c081fdffe523786 
1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an ARM MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "asm-printer"
15#include "ARMInstPrinter.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMAddressingModes.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25#define GET_INSTRUCTION_NAME
26#include "ARMGenAsmWriter.inc"
27
28/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
29///
30/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31static unsigned translateShiftImm(unsigned imm) {
32  if (imm == 0)
33    return 32;
34  return imm;
35}
36
37
38ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
39                               const MCSubtargetInfo &STI) :
40  MCInstPrinter(MAI) {
41  // Initialize the set of available features.
42  setAvailableFeatures(STI.getFeatureBits());
43}
44
45StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
46  return getInstructionName(Opcode);
47}
48
49void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
50  OS << getRegisterName(RegNo);
51}
52
53void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
54                               StringRef Annot) {
55  unsigned Opcode = MI->getOpcode();
56
57  // Check for MOVs and print canonical forms, instead.
58  if (Opcode == ARM::MOVsr) {
59    // FIXME: Thumb variants?
60    const MCOperand &Dst = MI->getOperand(0);
61    const MCOperand &MO1 = MI->getOperand(1);
62    const MCOperand &MO2 = MI->getOperand(2);
63    const MCOperand &MO3 = MI->getOperand(3);
64
65    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
66    printSBitModifierOperand(MI, 6, O);
67    printPredicateOperand(MI, 4, O);
68
69    O << '\t' << getRegisterName(Dst.getReg())
70      << ", " << getRegisterName(MO1.getReg());
71
72    O << ", " << getRegisterName(MO2.getReg());
73    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
74    printAnnotation(O, Annot);
75    return;
76  }
77
78  if (Opcode == ARM::MOVsi) {
79    // FIXME: Thumb variants?
80    const MCOperand &Dst = MI->getOperand(0);
81    const MCOperand &MO1 = MI->getOperand(1);
82    const MCOperand &MO2 = MI->getOperand(2);
83
84    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
85    printSBitModifierOperand(MI, 5, O);
86    printPredicateOperand(MI, 3, O);
87
88    O << '\t' << getRegisterName(Dst.getReg())
89      << ", " << getRegisterName(MO1.getReg());
90
91    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
92      printAnnotation(O, Annot);
93      return;
94    }
95
96    O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
97    printAnnotation(O, Annot);
98    return;
99  }
100
101
102  // A8.6.123 PUSH
103  if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
104      MI->getOperand(0).getReg() == ARM::SP) {
105    O << '\t' << "push";
106    printPredicateOperand(MI, 2, O);
107    if (Opcode == ARM::t2STMDB_UPD)
108      O << ".w";
109    O << '\t';
110    printRegisterList(MI, 4, O);
111    printAnnotation(O, Annot);
112    return;
113  }
114  if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
115      MI->getOperand(3).getImm() == -4) {
116    O << '\t' << "push";
117    printPredicateOperand(MI, 4, O);
118    O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
119    printAnnotation(O, Annot);
120    return;
121  }
122
123  // A8.6.122 POP
124  if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
125      MI->getOperand(0).getReg() == ARM::SP) {
126    O << '\t' << "pop";
127    printPredicateOperand(MI, 2, O);
128    if (Opcode == ARM::t2LDMIA_UPD)
129      O << ".w";
130    O << '\t';
131    printRegisterList(MI, 4, O);
132    printAnnotation(O, Annot);
133    return;
134  }
135  if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
136      MI->getOperand(4).getImm() == 4) {
137    O << '\t' << "pop";
138    printPredicateOperand(MI, 5, O);
139    O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
140    printAnnotation(O, Annot);
141    return;
142  }
143
144
145  // A8.6.355 VPUSH
146  if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
147      MI->getOperand(0).getReg() == ARM::SP) {
148    O << '\t' << "vpush";
149    printPredicateOperand(MI, 2, O);
150    O << '\t';
151    printRegisterList(MI, 4, O);
152    printAnnotation(O, Annot);
153    return;
154  }
155
156  // A8.6.354 VPOP
157  if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
158      MI->getOperand(0).getReg() == ARM::SP) {
159    O << '\t' << "vpop";
160    printPredicateOperand(MI, 2, O);
161    O << '\t';
162    printRegisterList(MI, 4, O);
163    printAnnotation(O, Annot);
164    return;
165  }
166
167  if (Opcode == ARM::tLDMIA) {
168    bool Writeback = true;
169    unsigned BaseReg = MI->getOperand(0).getReg();
170    for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
171      if (MI->getOperand(i).getReg() == BaseReg)
172        Writeback = false;
173    }
174
175    O << "\tldm";
176
177    printPredicateOperand(MI, 1, O);
178    O << '\t' << getRegisterName(BaseReg);
179    if (Writeback) O << "!";
180    O << ", ";
181    printRegisterList(MI, 3, O);
182    printAnnotation(O, Annot);
183    return;
184  }
185
186  // Thumb1 NOP
187  if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
188      MI->getOperand(1).getReg() == ARM::R8) {
189    O << "\tnop";
190    printPredicateOperand(MI, 2, O);
191    printAnnotation(O, Annot);
192    return;
193  }
194
195  printInstruction(MI, O);
196  printAnnotation(O, Annot);
197}
198
199void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
200                                  raw_ostream &O) {
201  const MCOperand &Op = MI->getOperand(OpNo);
202  if (Op.isReg()) {
203    unsigned Reg = Op.getReg();
204    O << getRegisterName(Reg);
205  } else if (Op.isImm()) {
206    O << '#' << Op.getImm();
207  } else {
208    assert(Op.isExpr() && "unknown operand kind in printOperand");
209    // If a symbolic branch target was added as a constant expression then print
210    // that address in hex.
211    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
212    int64_t Address;
213    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
214      O << "0x";
215      O.write_hex(Address);
216    }
217    else {
218      // Otherwise, just print the expression.
219      O << *Op.getExpr();
220    }
221  }
222}
223
224void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
225                                       raw_ostream &O) {
226  const MCOperand &MO1 = MI->getOperand(OpNum);
227  if (MO1.isExpr())
228    O << *MO1.getExpr();
229  else if (MO1.isImm())
230    O << "[pc, #" << MO1.getImm() << "]";
231  else
232    llvm_unreachable("Unknown LDR label operand?");
233}
234
235// so_reg is a 4-operand unit corresponding to register forms of the A5.1
236// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
237//    REG 0   0           - e.g. R5
238//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
239//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
240void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
241                                       raw_ostream &O) {
242  const MCOperand &MO1 = MI->getOperand(OpNum);
243  const MCOperand &MO2 = MI->getOperand(OpNum+1);
244  const MCOperand &MO3 = MI->getOperand(OpNum+2);
245
246  O << getRegisterName(MO1.getReg());
247
248  // Print the shift opc.
249  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
250  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
251  if (ShOpc == ARM_AM::rrx)
252    return;
253
254  O << ' ' << getRegisterName(MO2.getReg());
255  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
256}
257
258void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
259                                       raw_ostream &O) {
260  const MCOperand &MO1 = MI->getOperand(OpNum);
261  const MCOperand &MO2 = MI->getOperand(OpNum+1);
262
263  O << getRegisterName(MO1.getReg());
264
265  // Print the shift opc.
266  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
267  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
268  if (ShOpc == ARM_AM::rrx)
269    return;
270  O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
271}
272
273
274//===--------------------------------------------------------------------===//
275// Addressing Mode #2
276//===--------------------------------------------------------------------===//
277
278void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
279                                                raw_ostream &O) {
280  const MCOperand &MO1 = MI->getOperand(Op);
281  const MCOperand &MO2 = MI->getOperand(Op+1);
282  const MCOperand &MO3 = MI->getOperand(Op+2);
283
284  O << "[" << getRegisterName(MO1.getReg());
285
286  if (!MO2.getReg()) {
287    if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
288      O << ", #"
289        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
290        << ARM_AM::getAM2Offset(MO3.getImm());
291    O << "]";
292    return;
293  }
294
295  O << ", "
296    << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
297    << getRegisterName(MO2.getReg());
298
299  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
300    O << ", "
301    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
302    << " #" << ShImm;
303  O << "]";
304}
305
306void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
307                                         raw_ostream &O) {
308  const MCOperand &MO1 = MI->getOperand(Op);
309  const MCOperand &MO2 = MI->getOperand(Op+1);
310  const MCOperand &MO3 = MI->getOperand(Op+2);
311
312  O << "[" << getRegisterName(MO1.getReg()) << "], ";
313
314  if (!MO2.getReg()) {
315    unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
316    O << '#'
317      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
318      << ImmOffs;
319    return;
320  }
321
322  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
323    << getRegisterName(MO2.getReg());
324
325  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
326    O << ", "
327    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
328    << " #" << ShImm;
329}
330
331void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
332                                           raw_ostream &O) {
333  const MCOperand &MO1 = MI->getOperand(Op);
334  const MCOperand &MO2 = MI->getOperand(Op+1);
335  O << "[" << getRegisterName(MO1.getReg()) << ", "
336    << getRegisterName(MO2.getReg()) << "]";
337}
338
339void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
340                                           raw_ostream &O) {
341  const MCOperand &MO1 = MI->getOperand(Op);
342  const MCOperand &MO2 = MI->getOperand(Op+1);
343  O << "[" << getRegisterName(MO1.getReg()) << ", "
344    << getRegisterName(MO2.getReg()) << ", lsl #1]";
345}
346
347void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
348                                           raw_ostream &O) {
349  const MCOperand &MO1 = MI->getOperand(Op);
350
351  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
352    printOperand(MI, Op, O);
353    return;
354  }
355
356  const MCOperand &MO3 = MI->getOperand(Op+2);
357  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
358
359  if (IdxMode == ARMII::IndexModePost) {
360    printAM2PostIndexOp(MI, Op, O);
361    return;
362  }
363  printAM2PreOrOffsetIndexOp(MI, Op, O);
364}
365
366void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
367                                                 unsigned OpNum,
368                                                 raw_ostream &O) {
369  const MCOperand &MO1 = MI->getOperand(OpNum);
370  const MCOperand &MO2 = MI->getOperand(OpNum+1);
371
372  if (!MO1.getReg()) {
373    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
374    O << '#'
375      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
376      << ImmOffs;
377    return;
378  }
379
380  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
381    << getRegisterName(MO1.getReg());
382
383  if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
384    O << ", "
385    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
386    << " #" << ShImm;
387}
388
389//===--------------------------------------------------------------------===//
390// Addressing Mode #3
391//===--------------------------------------------------------------------===//
392
393void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
394                                         raw_ostream &O) {
395  const MCOperand &MO1 = MI->getOperand(Op);
396  const MCOperand &MO2 = MI->getOperand(Op+1);
397  const MCOperand &MO3 = MI->getOperand(Op+2);
398
399  O << "[" << getRegisterName(MO1.getReg()) << "], ";
400
401  if (MO2.getReg()) {
402    O << (char)ARM_AM::getAM3Op(MO3.getImm())
403    << getRegisterName(MO2.getReg());
404    return;
405  }
406
407  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
408  O << '#'
409    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
410    << ImmOffs;
411}
412
413void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
414                                                raw_ostream &O) {
415  const MCOperand &MO1 = MI->getOperand(Op);
416  const MCOperand &MO2 = MI->getOperand(Op+1);
417  const MCOperand &MO3 = MI->getOperand(Op+2);
418
419  O << '[' << getRegisterName(MO1.getReg());
420
421  if (MO2.getReg()) {
422    O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
423      << getRegisterName(MO2.getReg()) << ']';
424    return;
425  }
426
427  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
428    O << ", #"
429      << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
430      << ImmOffs;
431  O << ']';
432}
433
434void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
435                                           raw_ostream &O) {
436  const MCOperand &MO3 = MI->getOperand(Op+2);
437  unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
438
439  if (IdxMode == ARMII::IndexModePost) {
440    printAM3PostIndexOp(MI, Op, O);
441    return;
442  }
443  printAM3PreOrOffsetIndexOp(MI, Op, O);
444}
445
446void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
447                                                 unsigned OpNum,
448                                                 raw_ostream &O) {
449  const MCOperand &MO1 = MI->getOperand(OpNum);
450  const MCOperand &MO2 = MI->getOperand(OpNum+1);
451
452  if (MO1.getReg()) {
453    O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
454      << getRegisterName(MO1.getReg());
455    return;
456  }
457
458  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
459  O << '#'
460    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
461    << ImmOffs;
462}
463
464void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
465                                             unsigned OpNum,
466                                             raw_ostream &O) {
467  const MCOperand &MO = MI->getOperand(OpNum);
468  unsigned Imm = MO.getImm();
469  O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
470}
471
472void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
473                                            raw_ostream &O) {
474  const MCOperand &MO1 = MI->getOperand(OpNum);
475  const MCOperand &MO2 = MI->getOperand(OpNum+1);
476
477  O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
478}
479
480void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
481                                             unsigned OpNum,
482                                             raw_ostream &O) {
483  const MCOperand &MO = MI->getOperand(OpNum);
484  unsigned Imm = MO.getImm();
485  O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
486}
487
488
489void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
490                                           raw_ostream &O) {
491  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
492                                                 .getImm());
493  O << ARM_AM::getAMSubModeStr(Mode);
494}
495
496void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
497                                           raw_ostream &O) {
498  const MCOperand &MO1 = MI->getOperand(OpNum);
499  const MCOperand &MO2 = MI->getOperand(OpNum+1);
500
501  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
502    printOperand(MI, OpNum, O);
503    return;
504  }
505
506  O << "[" << getRegisterName(MO1.getReg());
507
508  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
509  unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
510  if (ImmOffs || Op == ARM_AM::sub) {
511    O << ", #"
512      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
513      << ImmOffs * 4;
514  }
515  O << "]";
516}
517
518void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
519                                           raw_ostream &O) {
520  const MCOperand &MO1 = MI->getOperand(OpNum);
521  const MCOperand &MO2 = MI->getOperand(OpNum+1);
522
523  O << "[" << getRegisterName(MO1.getReg());
524  if (MO2.getImm()) {
525    // FIXME: Both darwin as and GNU as violate ARM docs here.
526    O << ", :" << (MO2.getImm() << 3);
527  }
528  O << "]";
529}
530
531void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
532                                           raw_ostream &O) {
533  const MCOperand &MO1 = MI->getOperand(OpNum);
534  O << "[" << getRegisterName(MO1.getReg()) << "]";
535}
536
537void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
538                                                 unsigned OpNum,
539                                                 raw_ostream &O) {
540  const MCOperand &MO = MI->getOperand(OpNum);
541  if (MO.getReg() == 0)
542    O << "!";
543  else
544    O << ", " << getRegisterName(MO.getReg());
545}
546
547void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
548                                                    unsigned OpNum,
549                                                    raw_ostream &O) {
550  const MCOperand &MO = MI->getOperand(OpNum);
551  uint32_t v = ~MO.getImm();
552  int32_t lsb = CountTrailingZeros_32(v);
553  int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
554  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
555  O << '#' << lsb << ", #" << width;
556}
557
558void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
559                                     raw_ostream &O) {
560  unsigned val = MI->getOperand(OpNum).getImm();
561  O << ARM_MB::MemBOptToString(val);
562}
563
564void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
565                                          raw_ostream &O) {
566  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
567  bool isASR = (ShiftOp & (1 << 5)) != 0;
568  unsigned Amt = ShiftOp & 0x1f;
569  if (isASR)
570    O << ", asr #" << (Amt == 0 ? 32 : Amt);
571  else if (Amt)
572    O << ", lsl #" << Amt;
573}
574
575void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
576                                         raw_ostream &O) {
577  unsigned Imm = MI->getOperand(OpNum).getImm();
578  if (Imm == 0)
579    return;
580  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
581  O << ", lsl #" << Imm;
582}
583
584void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
585                                         raw_ostream &O) {
586  unsigned Imm = MI->getOperand(OpNum).getImm();
587  // A shift amount of 32 is encoded as 0.
588  if (Imm == 0)
589    Imm = 32;
590  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
591  O << ", asr #" << Imm;
592}
593
594void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
595                                       raw_ostream &O) {
596  O << "{";
597  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
598    if (i != OpNum) O << ", ";
599    O << getRegisterName(MI->getOperand(i).getReg());
600  }
601  O << "}";
602}
603
604void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
605                                        raw_ostream &O) {
606  const MCOperand &Op = MI->getOperand(OpNum);
607  if (Op.getImm())
608    O << "be";
609  else
610    O << "le";
611}
612
613void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
614                                  raw_ostream &O) {
615  const MCOperand &Op = MI->getOperand(OpNum);
616  O << ARM_PROC::IModToString(Op.getImm());
617}
618
619void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
620                                   raw_ostream &O) {
621  const MCOperand &Op = MI->getOperand(OpNum);
622  unsigned IFlags = Op.getImm();
623  for (int i=2; i >= 0; --i)
624    if (IFlags & (1 << i))
625      O << ARM_PROC::IFlagsToString(1 << i);
626
627  if (IFlags == 0)
628    O << "none";
629}
630
631void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
632                                         raw_ostream &O) {
633  const MCOperand &Op = MI->getOperand(OpNum);
634  unsigned SpecRegRBit = Op.getImm() >> 4;
635  unsigned Mask = Op.getImm() & 0xf;
636
637  if (getAvailableFeatures() & ARM::FeatureMClass) {
638    switch (Op.getImm()) {
639    default: assert(0 && "Unexpected mask value!");
640    case 0: O << "apsr"; return;
641    case 1: O << "iapsr"; return;
642    case 2: O << "eapsr"; return;
643    case 3: O << "xpsr"; return;
644    case 5: O << "ipsr"; return;
645    case 6: O << "epsr"; return;
646    case 7: O << "iepsr"; return;
647    case 8: O << "msp"; return;
648    case 9: O << "psp"; return;
649    case 16: O << "primask"; return;
650    case 17: O << "basepri"; return;
651    case 18: O << "basepri_max"; return;
652    case 19: O << "faultmask"; return;
653    case 20: O << "control"; return;
654    }
655  }
656
657  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
658  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
659  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
660    O << "APSR_";
661    switch (Mask) {
662    default: assert(0);
663    case 4:  O << "g"; return;
664    case 8:  O << "nzcvq"; return;
665    case 12: O << "nzcvqg"; return;
666    }
667    llvm_unreachable("Unexpected mask value!");
668  }
669
670  if (SpecRegRBit)
671    O << "SPSR";
672  else
673    O << "CPSR";
674
675  if (Mask) {
676    O << '_';
677    if (Mask & 8) O << 'f';
678    if (Mask & 4) O << 's';
679    if (Mask & 2) O << 'x';
680    if (Mask & 1) O << 'c';
681  }
682}
683
684void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
685                                           raw_ostream &O) {
686  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
687  if (CC != ARMCC::AL)
688    O << ARMCondCodeToString(CC);
689}
690
691void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
692                                                    unsigned OpNum,
693                                                    raw_ostream &O) {
694  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
695  O << ARMCondCodeToString(CC);
696}
697
698void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
699                                              raw_ostream &O) {
700  if (MI->getOperand(OpNum).getReg()) {
701    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
702           "Expect ARM CPSR register!");
703    O << 's';
704  }
705}
706
707void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
708                                          raw_ostream &O) {
709  O << MI->getOperand(OpNum).getImm();
710}
711
712void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
713                                     raw_ostream &O) {
714  O << "p" << MI->getOperand(OpNum).getImm();
715}
716
717void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
718                                     raw_ostream &O) {
719  O << "c" << MI->getOperand(OpNum).getImm();
720}
721
722void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
723                                  raw_ostream &O) {
724  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
725}
726
727void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
728                                            raw_ostream &O) {
729  O << "#" << MI->getOperand(OpNum).getImm() * 4;
730}
731
732void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
733                                     raw_ostream &O) {
734  unsigned Imm = MI->getOperand(OpNum).getImm();
735  O << "#" << (Imm == 0 ? 32 : Imm);
736}
737
738void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
739                                      raw_ostream &O) {
740  // (3 - the number of trailing zeros) is the number of then / else.
741  unsigned Mask = MI->getOperand(OpNum).getImm();
742  unsigned CondBit0 = Mask >> 4 & 1;
743  unsigned NumTZ = CountTrailingZeros_32(Mask);
744  assert(NumTZ <= 3 && "Invalid IT mask!");
745  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
746    bool T = ((Mask >> Pos) & 1) == CondBit0;
747    if (T)
748      O << 't';
749    else
750      O << 'e';
751  }
752}
753
754void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
755                                                 raw_ostream &O) {
756  const MCOperand &MO1 = MI->getOperand(Op);
757  const MCOperand &MO2 = MI->getOperand(Op + 1);
758
759  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
760    printOperand(MI, Op, O);
761    return;
762  }
763
764  O << "[" << getRegisterName(MO1.getReg());
765  if (unsigned RegNum = MO2.getReg())
766    O << ", " << getRegisterName(RegNum);
767  O << "]";
768}
769
770void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
771                                                    unsigned Op,
772                                                    raw_ostream &O,
773                                                    unsigned Scale) {
774  const MCOperand &MO1 = MI->getOperand(Op);
775  const MCOperand &MO2 = MI->getOperand(Op + 1);
776
777  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
778    printOperand(MI, Op, O);
779    return;
780  }
781
782  O << "[" << getRegisterName(MO1.getReg());
783  if (unsigned ImmOffs = MO2.getImm())
784    O << ", #" << ImmOffs * Scale;
785  O << "]";
786}
787
788void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
789                                                     unsigned Op,
790                                                     raw_ostream &O) {
791  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
792}
793
794void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
795                                                     unsigned Op,
796                                                     raw_ostream &O) {
797  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
798}
799
800void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
801                                                     unsigned Op,
802                                                     raw_ostream &O) {
803  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
804}
805
806void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
807                                                 raw_ostream &O) {
808  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
809}
810
811// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
812// register with shift forms.
813// REG 0   0           - e.g. R5
814// REG IMM, SH_OPC     - e.g. R5, LSL #3
815void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
816                                      raw_ostream &O) {
817  const MCOperand &MO1 = MI->getOperand(OpNum);
818  const MCOperand &MO2 = MI->getOperand(OpNum+1);
819
820  unsigned Reg = MO1.getReg();
821  O << getRegisterName(Reg);
822
823  // Print the shift opc.
824  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
825  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
826  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
827  if (ShOpc != ARM_AM::rrx)
828    O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
829}
830
831void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
832                                               raw_ostream &O) {
833  const MCOperand &MO1 = MI->getOperand(OpNum);
834  const MCOperand &MO2 = MI->getOperand(OpNum+1);
835
836  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
837    printOperand(MI, OpNum, O);
838    return;
839  }
840
841  O << "[" << getRegisterName(MO1.getReg());
842
843  int32_t OffImm = (int32_t)MO2.getImm();
844  bool isSub = OffImm < 0;
845  // Special value for #-0. All others are normal.
846  if (OffImm == INT32_MIN)
847    OffImm = 0;
848  if (isSub)
849    O << ", #-" << -OffImm;
850  else if (OffImm > 0)
851    O << ", #" << OffImm;
852  O << "]";
853}
854
855void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
856                                                unsigned OpNum,
857                                                raw_ostream &O) {
858  const MCOperand &MO1 = MI->getOperand(OpNum);
859  const MCOperand &MO2 = MI->getOperand(OpNum+1);
860
861  O << "[" << getRegisterName(MO1.getReg());
862
863  int32_t OffImm = (int32_t)MO2.getImm();
864  // Don't print +0.
865  if (OffImm == INT32_MIN)
866    O << ", #-0";
867  else if (OffImm < 0)
868    O << ", #-" << -OffImm;
869  else if (OffImm > 0)
870    O << ", #" << OffImm;
871  O << "]";
872}
873
874void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
875                                                  unsigned OpNum,
876                                                  raw_ostream &O) {
877  const MCOperand &MO1 = MI->getOperand(OpNum);
878  const MCOperand &MO2 = MI->getOperand(OpNum+1);
879
880  O << "[" << getRegisterName(MO1.getReg());
881
882  int32_t OffImm = (int32_t)MO2.getImm() / 4;
883  // Don't print +0.
884  if (OffImm < 0)
885    O << ", #-" << -OffImm * 4;
886  else if (OffImm > 0)
887    O << ", #" << OffImm * 4;
888  O << "]";
889}
890
891void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
892                                                       unsigned OpNum,
893                                                       raw_ostream &O) {
894  const MCOperand &MO1 = MI->getOperand(OpNum);
895  const MCOperand &MO2 = MI->getOperand(OpNum+1);
896
897  O << "[" << getRegisterName(MO1.getReg());
898  if (MO2.getImm())
899    O << ", #" << MO2.getImm() * 4;
900  O << "]";
901}
902
903void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
904                                                      unsigned OpNum,
905                                                      raw_ostream &O) {
906  const MCOperand &MO1 = MI->getOperand(OpNum);
907  int32_t OffImm = (int32_t)MO1.getImm();
908  // Don't print +0.
909  if (OffImm < 0)
910    O << ", #-" << -OffImm;
911  else
912    O << ", #" << OffImm;
913}
914
915void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
916                                                        unsigned OpNum,
917                                                        raw_ostream &O) {
918  const MCOperand &MO1 = MI->getOperand(OpNum);
919  int32_t OffImm = (int32_t)MO1.getImm() / 4;
920  // Don't print +0.
921  if (OffImm != 0) {
922    O << ", ";
923    if (OffImm < 0)
924      O << "#-" << -OffImm * 4;
925    else if (OffImm > 0)
926      O << "#" << OffImm * 4;
927  }
928}
929
930void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
931                                                 unsigned OpNum,
932                                                 raw_ostream &O) {
933  const MCOperand &MO1 = MI->getOperand(OpNum);
934  const MCOperand &MO2 = MI->getOperand(OpNum+1);
935  const MCOperand &MO3 = MI->getOperand(OpNum+2);
936
937  O << "[" << getRegisterName(MO1.getReg());
938
939  assert(MO2.getReg() && "Invalid so_reg load / store address!");
940  O << ", " << getRegisterName(MO2.getReg());
941
942  unsigned ShAmt = MO3.getImm();
943  if (ShAmt) {
944    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
945    O << ", lsl #" << ShAmt;
946  }
947  O << "]";
948}
949
950void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
951                                       raw_ostream &O) {
952  const MCOperand &MO = MI->getOperand(OpNum);
953  O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
954}
955
956void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
957                                            raw_ostream &O) {
958  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
959  unsigned EltBits;
960  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
961  O << "#0x" << utohexstr(Val);
962}
963
964void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
965                                            raw_ostream &O) {
966  unsigned Imm = MI->getOperand(OpNum).getImm();
967  O << "#" << Imm + 1;
968}
969
970void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
971                                        raw_ostream &O) {
972  unsigned Imm = MI->getOperand(OpNum).getImm();
973  if (Imm == 0)
974    return;
975  O << ", ror #";
976  switch (Imm) {
977  default: assert (0 && "illegal ror immediate!");
978  case 1: O << "8"; break;
979  case 2: O << "16"; break;
980  case 3: O << "24"; break;
981  }
982}
983
984void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
985                                      raw_ostream &O) {
986  O << "[" << MI->getOperand(OpNum).getImm() << "]";
987}
988