ARMInstPrinter.cpp revision 6274ec48b3a3e1fbaf3a359868d53a76f20a4245 
1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an ARM MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "asm-printer"
15#include "ARMBaseInfo.h"
16#include "ARMInstPrinter.h"
17#include "ARMAddressingModes.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25#define GET_INSTRUCTION_NAME
26#include "ARMGenAsmWriter.inc"
27
28StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29  return getInstructionName(Opcode);
30}
31
32
33void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
34  // Check for MOVs and print canonical forms, instead.
35  if (MI->getOpcode() == ARM::MOVs) {
36    // FIXME: Thumb variants?
37    const MCOperand &Dst = MI->getOperand(0);
38    const MCOperand &MO1 = MI->getOperand(1);
39    const MCOperand &MO2 = MI->getOperand(2);
40    const MCOperand &MO3 = MI->getOperand(3);
41
42    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
43    printSBitModifierOperand(MI, 6, O);
44    printPredicateOperand(MI, 4, O);
45
46    O << '\t' << getRegisterName(Dst.getReg())
47      << ", " << getRegisterName(MO1.getReg());
48
49    if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
50      return;
51
52    O << ", ";
53
54    if (MO2.getReg()) {
55      O << getRegisterName(MO2.getReg());
56      assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
57    } else {
58      O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
59    }
60    return;
61  }
62
63  // A8.6.123 PUSH
64  if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
65      MI->getOperand(0).getReg() == ARM::SP) {
66    const MCOperand &MO1 = MI->getOperand(2);
67    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
68      O << '\t' << "push";
69      printPredicateOperand(MI, 3, O);
70      O << '\t';
71      printRegisterList(MI, 5, O);
72      return;
73    }
74  }
75
76  // A8.6.122 POP
77  if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
78      MI->getOperand(0).getReg() == ARM::SP) {
79    const MCOperand &MO1 = MI->getOperand(2);
80    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
81      O << '\t' << "pop";
82      printPredicateOperand(MI, 3, O);
83      O << '\t';
84      printRegisterList(MI, 5, O);
85      return;
86    }
87  }
88
89  // A8.6.355 VPUSH
90  if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
91      MI->getOperand(0).getReg() == ARM::SP) {
92    const MCOperand &MO1 = MI->getOperand(2);
93    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
94      O << '\t' << "vpush";
95      printPredicateOperand(MI, 3, O);
96      O << '\t';
97      printRegisterList(MI, 5, O);
98      return;
99    }
100  }
101
102  // A8.6.354 VPOP
103  if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
104      MI->getOperand(0).getReg() == ARM::SP) {
105    const MCOperand &MO1 = MI->getOperand(2);
106    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
107      O << '\t' << "vpop";
108      printPredicateOperand(MI, 3, O);
109      O << '\t';
110      printRegisterList(MI, 5, O);
111      return;
112    }
113  }
114
115  printInstruction(MI, O);
116 }
117
118void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
119                                  raw_ostream &O, const char *Modifier) {
120  const MCOperand &Op = MI->getOperand(OpNo);
121  if (Op.isReg()) {
122    unsigned Reg = Op.getReg();
123    O << getRegisterName(Reg);
124  } else if (Op.isImm()) {
125    assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
126    O << '#' << Op.getImm();
127  } else {
128    assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
129    assert(Op.isExpr() && "unknown operand kind in printOperand");
130    O << *Op.getExpr();
131  }
132}
133
134static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
135                       const MCAsmInfo *MAI) {
136  // Break it up into two parts that make up a shifter immediate.
137  V = ARM_AM::getSOImmVal(V);
138  assert(V != -1 && "Not a valid so_imm value!");
139
140  unsigned Imm = ARM_AM::getSOImmValImm(V);
141  unsigned Rot = ARM_AM::getSOImmValRot(V);
142
143  // Print low-level immediate formation info, per
144  // A5.1.3: "Data-processing operands - Immediate".
145  if (Rot) {
146    O << "#" << Imm << ", " << Rot;
147    // Pretty printed version.
148    if (CommentStream)
149      *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
150  } else {
151    O << "#" << Imm;
152  }
153}
154
155
156/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
157/// immediate in bits 0-7.
158void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
159                                       raw_ostream &O) {
160  const MCOperand &MO = MI->getOperand(OpNum);
161  assert(MO.isImm() && "Not a valid so_imm value!");
162  printSOImm(O, MO.getImm(), CommentStream, &MAI);
163}
164
165/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
166/// followed by an 'orr' to materialize.
167void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
168                                            raw_ostream &O) {
169  // FIXME: REMOVE this method.
170  abort();
171}
172
173// so_reg is a 4-operand unit corresponding to register forms of the A5.1
174// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
175//    REG 0   0           - e.g. R5
176//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
177//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
178void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
179                                       raw_ostream &O) {
180  const MCOperand &MO1 = MI->getOperand(OpNum);
181  const MCOperand &MO2 = MI->getOperand(OpNum+1);
182  const MCOperand &MO3 = MI->getOperand(OpNum+2);
183
184  O << getRegisterName(MO1.getReg());
185
186  // Print the shift opc.
187  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
188  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
189  if (MO2.getReg()) {
190    O << ' ' << getRegisterName(MO2.getReg());
191    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
192  } else if (ShOpc != ARM_AM::rrx) {
193    O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
194  }
195}
196
197
198void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
199                                           raw_ostream &O) {
200  const MCOperand &MO1 = MI->getOperand(Op);
201  const MCOperand &MO2 = MI->getOperand(Op+1);
202  const MCOperand &MO3 = MI->getOperand(Op+2);
203
204  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
205    printOperand(MI, Op, O);
206    return;
207  }
208
209  O << "[" << getRegisterName(MO1.getReg());
210
211  if (!MO2.getReg()) {
212    if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
213      O << ", #"
214        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
215        << ARM_AM::getAM2Offset(MO3.getImm());
216    O << "]";
217    return;
218  }
219
220  O << ", "
221    << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
222    << getRegisterName(MO2.getReg());
223
224  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
225    O << ", "
226    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
227    << " #" << ShImm;
228  O << "]";
229}
230
231void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
232                                                 unsigned OpNum,
233                                                 raw_ostream &O) {
234  const MCOperand &MO1 = MI->getOperand(OpNum);
235  const MCOperand &MO2 = MI->getOperand(OpNum+1);
236
237  if (!MO1.getReg()) {
238    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
239    O << '#'
240      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
241      << ImmOffs;
242    return;
243  }
244
245  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
246    << getRegisterName(MO1.getReg());
247
248  if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
249    O << ", "
250    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
251    << " #" << ShImm;
252}
253
254void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
255                                           raw_ostream &O) {
256  const MCOperand &MO1 = MI->getOperand(OpNum);
257  const MCOperand &MO2 = MI->getOperand(OpNum+1);
258  const MCOperand &MO3 = MI->getOperand(OpNum+2);
259
260  O << '[' << getRegisterName(MO1.getReg());
261
262  if (MO2.getReg()) {
263    O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
264      << getRegisterName(MO2.getReg()) << ']';
265    return;
266  }
267
268  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
269    O << ", #"
270      << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
271      << ImmOffs;
272  O << ']';
273}
274
275void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
276                                                 unsigned OpNum,
277                                                 raw_ostream &O) {
278  const MCOperand &MO1 = MI->getOperand(OpNum);
279  const MCOperand &MO2 = MI->getOperand(OpNum+1);
280
281  if (MO1.getReg()) {
282    O << (char)ARM_AM::getAM3Op(MO2.getImm())
283    << getRegisterName(MO1.getReg());
284    return;
285  }
286
287  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
288  O << '#'
289    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
290    << ImmOffs;
291}
292
293
294void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
295                                           raw_ostream &O,
296                                           const char *Modifier) {
297  const MCOperand &MO2 = MI->getOperand(OpNum+1);
298  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
299  if (Modifier && strcmp(Modifier, "submode") == 0) {
300    O << ARM_AM::getAMSubModeStr(Mode);
301  } else if (Modifier && strcmp(Modifier, "wide") == 0) {
302    ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
303    if (Mode == ARM_AM::ia)
304      O << ".w";
305  } else {
306    printOperand(MI, OpNum, O);
307  }
308}
309
310void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
311                                           raw_ostream &O,
312                                           const char *Modifier) {
313  const MCOperand &MO1 = MI->getOperand(OpNum);
314  const MCOperand &MO2 = MI->getOperand(OpNum+1);
315
316  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
317    printOperand(MI, OpNum, O);
318    return;
319  }
320
321  O << "[" << getRegisterName(MO1.getReg());
322
323  if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
324    O << ", #"
325      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
326      << ImmOffs*4;
327  }
328  O << "]";
329}
330
331void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
332                                           raw_ostream &O) {
333  const MCOperand &MO1 = MI->getOperand(OpNum);
334  const MCOperand &MO2 = MI->getOperand(OpNum+1);
335
336  O << "[" << getRegisterName(MO1.getReg());
337  if (MO2.getImm()) {
338    // FIXME: Both darwin as and GNU as violate ARM docs here.
339    O << ", :" << (MO2.getImm() << 3);
340  }
341  O << "]";
342}
343
344void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
345                                                 unsigned OpNum,
346                                                 raw_ostream &O) {
347  const MCOperand &MO = MI->getOperand(OpNum);
348  if (MO.getReg() == 0)
349    O << "!";
350  else
351    O << ", " << getRegisterName(MO.getReg());
352}
353
354void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
355                                            raw_ostream &O,
356                                            const char *Modifier) {
357  // All instructions using addrmodepc are pseudos and should have been
358  // handled explicitly in printInstructionThroughMCStreamer(). If one got
359  // here, it wasn't, so something's wrong.
360  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
361}
362
363void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
364                                                    unsigned OpNum,
365                                                    raw_ostream &O) {
366  const MCOperand &MO = MI->getOperand(OpNum);
367  uint32_t v = ~MO.getImm();
368  int32_t lsb = CountTrailingZeros_32(v);
369  int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
370  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
371  O << '#' << lsb << ", #" << width;
372}
373
374void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
375                                     raw_ostream &O) {
376  unsigned val = MI->getOperand(OpNum).getImm();
377  O << ARM_MB::MemBOptToString(val);
378}
379
380void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
381                                          raw_ostream &O) {
382  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
383  ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
384  switch (Opc) {
385  case ARM_AM::no_shift:
386    return;
387  case ARM_AM::lsl:
388    O << ", lsl #";
389    break;
390  case ARM_AM::asr:
391    O << ", asr #";
392    break;
393  default:
394    assert(0 && "unexpected shift opcode for shift immediate operand");
395  }
396  O << ARM_AM::getSORegOffset(ShiftOp);
397}
398
399void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
400                                       raw_ostream &O) {
401  O << "{";
402  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
403    if (i != OpNum) O << ", ";
404    O << getRegisterName(MI->getOperand(i).getReg());
405  }
406  O << "}";
407}
408
409void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
410                                        raw_ostream &O) {
411  const MCOperand &Op = MI->getOperand(OpNum);
412  if (Op.getImm())
413    O << "be";
414  else
415    O << "le";
416}
417
418void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
419                                           raw_ostream &O) {
420  const MCOperand &Op = MI->getOperand(OpNum);
421  unsigned option = Op.getImm();
422  unsigned mode = option & 31;
423  bool changemode = option >> 5 & 1;
424  unsigned AIF = option >> 6 & 7;
425  unsigned imod = option >> 9 & 3;
426  if (imod == 2)
427    O << "ie";
428  else if (imod == 3)
429    O << "id";
430  O << '\t';
431  if (imod > 1) {
432    if (AIF & 4) O << 'a';
433    if (AIF & 2) O << 'i';
434    if (AIF & 1) O << 'f';
435    if (AIF > 0 && changemode) O << ", ";
436  }
437  if (changemode)
438    O << '#' << mode;
439}
440
441void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
442                                         raw_ostream &O) {
443  const MCOperand &Op = MI->getOperand(OpNum);
444  unsigned Mask = Op.getImm();
445  if (Mask) {
446    O << '_';
447    if (Mask & 8) O << 'f';
448    if (Mask & 4) O << 's';
449    if (Mask & 2) O << 'x';
450    if (Mask & 1) O << 'c';
451  }
452}
453
454void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
455                                         raw_ostream &O) {
456  const MCOperand &Op = MI->getOperand(OpNum);
457  O << '#';
458  if (Op.getImm() < 0)
459    O << '-' << (-Op.getImm() - 1);
460  else
461    O << Op.getImm();
462}
463
464void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
465                                           raw_ostream &O) {
466  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
467  if (CC != ARMCC::AL)
468    O << ARMCondCodeToString(CC);
469}
470
471void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
472                                                    unsigned OpNum,
473                                                    raw_ostream &O) {
474  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
475  O << ARMCondCodeToString(CC);
476}
477
478void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
479                                              raw_ostream &O) {
480  if (MI->getOperand(OpNum).getReg()) {
481    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
482           "Expect ARM CPSR register!");
483    O << 's';
484  }
485}
486
487
488
489void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
490                                        raw_ostream &O,
491                                        const char *Modifier) {
492  // FIXME: remove this.
493  abort();
494}
495
496void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
497                                          raw_ostream &O) {
498  O << MI->getOperand(OpNum).getImm();
499}
500
501
502void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
503                                  raw_ostream &O) {
504  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
505}
506
507void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
508                                            raw_ostream &O) {
509  O << "#" <<  MI->getOperand(OpNum).getImm() * 4;
510}
511
512void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
513                                      raw_ostream &O) {
514  // (3 - the number of trailing zeros) is the number of then / else.
515  unsigned Mask = MI->getOperand(OpNum).getImm();
516  unsigned CondBit0 = Mask >> 4 & 1;
517  unsigned NumTZ = CountTrailingZeros_32(Mask);
518  assert(NumTZ <= 3 && "Invalid IT mask!");
519  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
520    bool T = ((Mask >> Pos) & 1) == CondBit0;
521    if (T)
522      O << 't';
523    else
524      O << 'e';
525  }
526}
527
528void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
529                                                 raw_ostream &O) {
530  const MCOperand &MO1 = MI->getOperand(Op);
531  const MCOperand &MO2 = MI->getOperand(Op+1);
532  O << "[" << getRegisterName(MO1.getReg());
533  O << ", " << getRegisterName(MO2.getReg()) << "]";
534}
535
536void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
537                                                  raw_ostream &O,
538                                                  unsigned Scale) {
539  const MCOperand &MO1 = MI->getOperand(Op);
540  const MCOperand &MO2 = MI->getOperand(Op+1);
541  const MCOperand &MO3 = MI->getOperand(Op+2);
542
543  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
544    printOperand(MI, Op, O);
545    return;
546  }
547
548  O << "[" << getRegisterName(MO1.getReg());
549  if (MO3.getReg())
550    O << ", " << getRegisterName(MO3.getReg());
551  else if (unsigned ImmOffs = MO2.getImm())
552    O << ", #" << ImmOffs * Scale;
553  O << "]";
554}
555
556void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
557                                                 raw_ostream &O) {
558  printThumbAddrModeRI5Operand(MI, Op, O, 1);
559}
560
561void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
562                                                 raw_ostream &O) {
563  printThumbAddrModeRI5Operand(MI, Op, O, 2);
564}
565
566void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
567                                                 raw_ostream &O) {
568  printThumbAddrModeRI5Operand(MI, Op, O, 4);
569}
570
571void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
572                                                 raw_ostream &O) {
573  const MCOperand &MO1 = MI->getOperand(Op);
574  const MCOperand &MO2 = MI->getOperand(Op+1);
575  O << "[" << getRegisterName(MO1.getReg());
576  if (unsigned ImmOffs = MO2.getImm())
577    O << ", #" << ImmOffs*4;
578  O << "]";
579}
580
581void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
582                                     raw_ostream &O) {
583  O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
584  if (MI->getOpcode() == ARM::t2TBH)
585    O << ", lsl #1";
586  O << ']';
587}
588
589// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
590// register with shift forms.
591// REG 0   0           - e.g. R5
592// REG IMM, SH_OPC     - e.g. R5, LSL #3
593void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
594                                      raw_ostream &O) {
595  const MCOperand &MO1 = MI->getOperand(OpNum);
596  const MCOperand &MO2 = MI->getOperand(OpNum+1);
597
598  unsigned Reg = MO1.getReg();
599  O << getRegisterName(Reg);
600
601  // Print the shift opc.
602  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
603  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
604  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
605  if (ShOpc != ARM_AM::rrx)
606    O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
607}
608
609void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
610                                               raw_ostream &O) {
611  const MCOperand &MO1 = MI->getOperand(OpNum);
612  const MCOperand &MO2 = MI->getOperand(OpNum+1);
613
614  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
615    printOperand(MI, OpNum, O);
616    return;
617  }
618
619  O << "[" << getRegisterName(MO1.getReg());
620
621  int32_t OffImm = (int32_t)MO2.getImm();
622  bool isSub = OffImm < 0;
623  // Special value for #-0. All others are normal.
624  if (OffImm == INT32_MIN)
625    OffImm = 0;
626  if (isSub)
627    O << ", #-" << -OffImm;
628  else if (OffImm > 0)
629    O << ", #" << OffImm;
630  O << "]";
631}
632
633void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
634                                                unsigned OpNum,
635                                                raw_ostream &O) {
636  const MCOperand &MO1 = MI->getOperand(OpNum);
637  const MCOperand &MO2 = MI->getOperand(OpNum+1);
638
639  O << "[" << getRegisterName(MO1.getReg());
640
641  int32_t OffImm = (int32_t)MO2.getImm();
642  // Don't print +0.
643  if (OffImm < 0)
644    O << ", #-" << -OffImm;
645  else if (OffImm > 0)
646    O << ", #" << OffImm;
647  O << "]";
648}
649
650void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
651                                                  unsigned OpNum,
652                                                  raw_ostream &O) {
653  const MCOperand &MO1 = MI->getOperand(OpNum);
654  const MCOperand &MO2 = MI->getOperand(OpNum+1);
655
656  O << "[" << getRegisterName(MO1.getReg());
657
658  int32_t OffImm = (int32_t)MO2.getImm() / 4;
659  // Don't print +0.
660  if (OffImm < 0)
661    O << ", #-" << -OffImm * 4;
662  else if (OffImm > 0)
663    O << ", #" << OffImm * 4;
664  O << "]";
665}
666
667void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
668                                                      unsigned OpNum,
669                                                      raw_ostream &O) {
670  const MCOperand &MO1 = MI->getOperand(OpNum);
671  int32_t OffImm = (int32_t)MO1.getImm();
672  // Don't print +0.
673  if (OffImm < 0)
674    O << "#-" << -OffImm;
675  else if (OffImm > 0)
676    O << "#" << OffImm;
677}
678
679void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
680                                                        unsigned OpNum,
681                                                        raw_ostream &O) {
682  const MCOperand &MO1 = MI->getOperand(OpNum);
683  int32_t OffImm = (int32_t)MO1.getImm() / 4;
684  // Don't print +0.
685  if (OffImm < 0)
686    O << "#-" << -OffImm * 4;
687  else if (OffImm > 0)
688    O << "#" << OffImm * 4;
689}
690
691void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
692                                                 unsigned OpNum,
693                                                 raw_ostream &O) {
694  const MCOperand &MO1 = MI->getOperand(OpNum);
695  const MCOperand &MO2 = MI->getOperand(OpNum+1);
696  const MCOperand &MO3 = MI->getOperand(OpNum+2);
697
698  O << "[" << getRegisterName(MO1.getReg());
699
700  assert(MO2.getReg() && "Invalid so_reg load / store address!");
701  O << ", " << getRegisterName(MO2.getReg());
702
703  unsigned ShAmt = MO3.getImm();
704  if (ShAmt) {
705    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
706    O << ", lsl #" << ShAmt;
707  }
708  O << "]";
709}
710
711void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
712                                           raw_ostream &O) {
713  O << '#' << (float)MI->getOperand(OpNum).getFPImm();
714}
715
716void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
717                                           raw_ostream &O) {
718  O << '#' << MI->getOperand(OpNum).getFPImm();
719}
720
721void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
722                                            raw_ostream &O) {
723  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
724  unsigned EltBits;
725  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
726  O << "#0x" << utohexstr(Val);
727}
728