ARMInstPrinter.cpp revision c3384c93c0e4c50da4ad093f08997507f9281c75 
1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an ARM MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "asm-printer"
15#include "ARMInstPrinter.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMAddressingModes.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25#define GET_INSTRUCTION_NAME
26#include "ARMGenAsmWriter.inc"
27
28/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
29///
30/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31static unsigned translateShiftImm(unsigned imm) {
32  if (imm == 0)
33    return 32;
34  return imm;
35}
36
37
38ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
39                               const MCRegisterInfo &MRI,
40                               const MCSubtargetInfo &STI) :
41  MCInstPrinter(MAI, MRI) {
42  // Initialize the set of available features.
43  setAvailableFeatures(STI.getFeatureBits());
44}
45
46StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
47  return getInstructionName(Opcode);
48}
49
50void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51  OS << getRegisterName(RegNo);
52}
53
54void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
55                               StringRef Annot) {
56  unsigned Opcode = MI->getOpcode();
57
58  // Check for MOVs and print canonical forms, instead.
59  if (Opcode == ARM::MOVsr) {
60    // FIXME: Thumb variants?
61    const MCOperand &Dst = MI->getOperand(0);
62    const MCOperand &MO1 = MI->getOperand(1);
63    const MCOperand &MO2 = MI->getOperand(2);
64    const MCOperand &MO3 = MI->getOperand(3);
65
66    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
67    printSBitModifierOperand(MI, 6, O);
68    printPredicateOperand(MI, 4, O);
69
70    O << '\t' << getRegisterName(Dst.getReg())
71      << ", " << getRegisterName(MO1.getReg());
72
73    O << ", " << getRegisterName(MO2.getReg());
74    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
75    printAnnotation(O, Annot);
76    return;
77  }
78
79  if (Opcode == ARM::MOVsi) {
80    // FIXME: Thumb variants?
81    const MCOperand &Dst = MI->getOperand(0);
82    const MCOperand &MO1 = MI->getOperand(1);
83    const MCOperand &MO2 = MI->getOperand(2);
84
85    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
86    printSBitModifierOperand(MI, 5, O);
87    printPredicateOperand(MI, 3, O);
88
89    O << '\t' << getRegisterName(Dst.getReg())
90      << ", " << getRegisterName(MO1.getReg());
91
92    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
93      printAnnotation(O, Annot);
94      return;
95    }
96
97    O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
98    printAnnotation(O, Annot);
99    return;
100  }
101
102
103  // A8.6.123 PUSH
104  if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
105      MI->getOperand(0).getReg() == ARM::SP &&
106      MI->getNumOperands() > 5) {
107    // Should only print PUSH if there are at least two registers in the list.
108    O << '\t' << "push";
109    printPredicateOperand(MI, 2, O);
110    if (Opcode == ARM::t2STMDB_UPD)
111      O << ".w";
112    O << '\t';
113    printRegisterList(MI, 4, O);
114    printAnnotation(O, Annot);
115    return;
116  }
117  if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
118      MI->getOperand(3).getImm() == -4) {
119    O << '\t' << "push";
120    printPredicateOperand(MI, 4, O);
121    O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
122    printAnnotation(O, Annot);
123    return;
124  }
125
126  // A8.6.122 POP
127  if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
128      MI->getOperand(0).getReg() == ARM::SP &&
129      MI->getNumOperands() > 5) {
130    // Should only print POP if there are at least two registers in the list.
131    O << '\t' << "pop";
132    printPredicateOperand(MI, 2, O);
133    if (Opcode == ARM::t2LDMIA_UPD)
134      O << ".w";
135    O << '\t';
136    printRegisterList(MI, 4, O);
137    printAnnotation(O, Annot);
138    return;
139  }
140  if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
141      MI->getOperand(4).getImm() == 4) {
142    O << '\t' << "pop";
143    printPredicateOperand(MI, 5, O);
144    O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
145    printAnnotation(O, Annot);
146    return;
147  }
148
149
150  // A8.6.355 VPUSH
151  if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
152      MI->getOperand(0).getReg() == ARM::SP) {
153    O << '\t' << "vpush";
154    printPredicateOperand(MI, 2, O);
155    O << '\t';
156    printRegisterList(MI, 4, O);
157    printAnnotation(O, Annot);
158    return;
159  }
160
161  // A8.6.354 VPOP
162  if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
163      MI->getOperand(0).getReg() == ARM::SP) {
164    O << '\t' << "vpop";
165    printPredicateOperand(MI, 2, O);
166    O << '\t';
167    printRegisterList(MI, 4, O);
168    printAnnotation(O, Annot);
169    return;
170  }
171
172  if (Opcode == ARM::tLDMIA) {
173    bool Writeback = true;
174    unsigned BaseReg = MI->getOperand(0).getReg();
175    for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
176      if (MI->getOperand(i).getReg() == BaseReg)
177        Writeback = false;
178    }
179
180    O << "\tldm";
181
182    printPredicateOperand(MI, 1, O);
183    O << '\t' << getRegisterName(BaseReg);
184    if (Writeback) O << "!";
185    O << ", ";
186    printRegisterList(MI, 3, O);
187    printAnnotation(O, Annot);
188    return;
189  }
190
191  // Thumb1 NOP
192  if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
193      MI->getOperand(1).getReg() == ARM::R8) {
194    O << "\tnop";
195    printPredicateOperand(MI, 2, O);
196    printAnnotation(O, Annot);
197    return;
198  }
199
200  printInstruction(MI, O);
201  printAnnotation(O, Annot);
202}
203
204void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
205                                  raw_ostream &O) {
206  const MCOperand &Op = MI->getOperand(OpNo);
207  if (Op.isReg()) {
208    unsigned Reg = Op.getReg();
209    O << getRegisterName(Reg);
210  } else if (Op.isImm()) {
211    O << '#' << Op.getImm();
212  } else {
213    assert(Op.isExpr() && "unknown operand kind in printOperand");
214    // If a symbolic branch target was added as a constant expression then print
215    // that address in hex.
216    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
217    int64_t Address;
218    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
219      O << "0x";
220      O.write_hex(Address);
221    }
222    else {
223      // Otherwise, just print the expression.
224      O << *Op.getExpr();
225    }
226  }
227}
228
229void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
230                                       raw_ostream &O) {
231  const MCOperand &MO1 = MI->getOperand(OpNum);
232  if (MO1.isExpr())
233    O << *MO1.getExpr();
234  else if (MO1.isImm())
235    O << "[pc, #" << MO1.getImm() << "]";
236  else
237    llvm_unreachable("Unknown LDR label operand?");
238}
239
240// so_reg is a 4-operand unit corresponding to register forms of the A5.1
241// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
242//    REG 0   0           - e.g. R5
243//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
244//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
245void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
246                                       raw_ostream &O) {
247  const MCOperand &MO1 = MI->getOperand(OpNum);
248  const MCOperand &MO2 = MI->getOperand(OpNum+1);
249  const MCOperand &MO3 = MI->getOperand(OpNum+2);
250
251  O << getRegisterName(MO1.getReg());
252
253  // Print the shift opc.
254  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
255  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
256  if (ShOpc == ARM_AM::rrx)
257    return;
258
259  O << ' ' << getRegisterName(MO2.getReg());
260  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
261}
262
263void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
264                                       raw_ostream &O) {
265  const MCOperand &MO1 = MI->getOperand(OpNum);
266  const MCOperand &MO2 = MI->getOperand(OpNum+1);
267
268  O << getRegisterName(MO1.getReg());
269
270  // Print the shift opc.
271  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
272  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
273  if (ShOpc == ARM_AM::rrx)
274    return;
275  O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
276}
277
278
279//===--------------------------------------------------------------------===//
280// Addressing Mode #2
281//===--------------------------------------------------------------------===//
282
283void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
284                                                raw_ostream &O) {
285  const MCOperand &MO1 = MI->getOperand(Op);
286  const MCOperand &MO2 = MI->getOperand(Op+1);
287  const MCOperand &MO3 = MI->getOperand(Op+2);
288
289  O << "[" << getRegisterName(MO1.getReg());
290
291  if (!MO2.getReg()) {
292    if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
293      O << ", #"
294        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
295        << ARM_AM::getAM2Offset(MO3.getImm());
296    O << "]";
297    return;
298  }
299
300  O << ", "
301    << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
302    << getRegisterName(MO2.getReg());
303
304  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
305    O << ", "
306    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
307    << " #" << ShImm;
308  O << "]";
309}
310
311void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
312                                         raw_ostream &O) {
313  const MCOperand &MO1 = MI->getOperand(Op);
314  const MCOperand &MO2 = MI->getOperand(Op+1);
315  const MCOperand &MO3 = MI->getOperand(Op+2);
316
317  O << "[" << getRegisterName(MO1.getReg()) << "], ";
318
319  if (!MO2.getReg()) {
320    unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
321    O << '#'
322      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
323      << ImmOffs;
324    return;
325  }
326
327  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
328    << getRegisterName(MO2.getReg());
329
330  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
331    O << ", "
332    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
333    << " #" << ShImm;
334}
335
336void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
337                                           raw_ostream &O) {
338  const MCOperand &MO1 = MI->getOperand(Op);
339  const MCOperand &MO2 = MI->getOperand(Op+1);
340  O << "[" << getRegisterName(MO1.getReg()) << ", "
341    << getRegisterName(MO2.getReg()) << "]";
342}
343
344void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
345                                           raw_ostream &O) {
346  const MCOperand &MO1 = MI->getOperand(Op);
347  const MCOperand &MO2 = MI->getOperand(Op+1);
348  O << "[" << getRegisterName(MO1.getReg()) << ", "
349    << getRegisterName(MO2.getReg()) << ", lsl #1]";
350}
351
352void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
353                                           raw_ostream &O) {
354  const MCOperand &MO1 = MI->getOperand(Op);
355
356  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
357    printOperand(MI, Op, O);
358    return;
359  }
360
361  const MCOperand &MO3 = MI->getOperand(Op+2);
362  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
363
364  if (IdxMode == ARMII::IndexModePost) {
365    printAM2PostIndexOp(MI, Op, O);
366    return;
367  }
368  printAM2PreOrOffsetIndexOp(MI, Op, O);
369}
370
371void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
372                                                 unsigned OpNum,
373                                                 raw_ostream &O) {
374  const MCOperand &MO1 = MI->getOperand(OpNum);
375  const MCOperand &MO2 = MI->getOperand(OpNum+1);
376
377  if (!MO1.getReg()) {
378    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
379    O << '#'
380      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
381      << ImmOffs;
382    return;
383  }
384
385  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
386    << getRegisterName(MO1.getReg());
387
388  if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
389    O << ", "
390    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
391    << " #" << ShImm;
392}
393
394//===--------------------------------------------------------------------===//
395// Addressing Mode #3
396//===--------------------------------------------------------------------===//
397
398void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
399                                         raw_ostream &O) {
400  const MCOperand &MO1 = MI->getOperand(Op);
401  const MCOperand &MO2 = MI->getOperand(Op+1);
402  const MCOperand &MO3 = MI->getOperand(Op+2);
403
404  O << "[" << getRegisterName(MO1.getReg()) << "], ";
405
406  if (MO2.getReg()) {
407    O << (char)ARM_AM::getAM3Op(MO3.getImm())
408    << getRegisterName(MO2.getReg());
409    return;
410  }
411
412  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
413  O << '#'
414    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
415    << ImmOffs;
416}
417
418void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
419                                                raw_ostream &O) {
420  const MCOperand &MO1 = MI->getOperand(Op);
421  const MCOperand &MO2 = MI->getOperand(Op+1);
422  const MCOperand &MO3 = MI->getOperand(Op+2);
423
424  O << '[' << getRegisterName(MO1.getReg());
425
426  if (MO2.getReg()) {
427    O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
428      << getRegisterName(MO2.getReg()) << ']';
429    return;
430  }
431
432  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
433    O << ", #"
434      << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
435      << ImmOffs;
436  O << ']';
437}
438
439void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
440                                           raw_ostream &O) {
441  const MCOperand &MO1 = MI->getOperand(Op);
442  if (!MO1.isReg()) {   //  For label symbolic references.
443    printOperand(MI, Op, O);
444    return;
445  }
446
447  const MCOperand &MO3 = MI->getOperand(Op+2);
448  unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
449
450  if (IdxMode == ARMII::IndexModePost) {
451    printAM3PostIndexOp(MI, Op, O);
452    return;
453  }
454  printAM3PreOrOffsetIndexOp(MI, Op, O);
455}
456
457void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
458                                                 unsigned OpNum,
459                                                 raw_ostream &O) {
460  const MCOperand &MO1 = MI->getOperand(OpNum);
461  const MCOperand &MO2 = MI->getOperand(OpNum+1);
462
463  if (MO1.getReg()) {
464    O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
465      << getRegisterName(MO1.getReg());
466    return;
467  }
468
469  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
470  O << '#'
471    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
472    << ImmOffs;
473}
474
475void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
476                                             unsigned OpNum,
477                                             raw_ostream &O) {
478  const MCOperand &MO = MI->getOperand(OpNum);
479  unsigned Imm = MO.getImm();
480  O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
481}
482
483void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
484                                            raw_ostream &O) {
485  const MCOperand &MO1 = MI->getOperand(OpNum);
486  const MCOperand &MO2 = MI->getOperand(OpNum+1);
487
488  O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
489}
490
491void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
492                                             unsigned OpNum,
493                                             raw_ostream &O) {
494  const MCOperand &MO = MI->getOperand(OpNum);
495  unsigned Imm = MO.getImm();
496  O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
497}
498
499
500void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
501                                           raw_ostream &O) {
502  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
503                                                 .getImm());
504  O << ARM_AM::getAMSubModeStr(Mode);
505}
506
507void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
508                                           raw_ostream &O) {
509  const MCOperand &MO1 = MI->getOperand(OpNum);
510  const MCOperand &MO2 = MI->getOperand(OpNum+1);
511
512  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
513    printOperand(MI, OpNum, O);
514    return;
515  }
516
517  O << "[" << getRegisterName(MO1.getReg());
518
519  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
520  unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
521  if (ImmOffs || Op == ARM_AM::sub) {
522    O << ", #"
523      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
524      << ImmOffs * 4;
525  }
526  O << "]";
527}
528
529void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
530                                           raw_ostream &O) {
531  const MCOperand &MO1 = MI->getOperand(OpNum);
532  const MCOperand &MO2 = MI->getOperand(OpNum+1);
533
534  O << "[" << getRegisterName(MO1.getReg());
535  if (MO2.getImm()) {
536    // FIXME: Both darwin as and GNU as violate ARM docs here.
537    O << ", :" << (MO2.getImm() << 3);
538  }
539  O << "]";
540}
541
542void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
543                                           raw_ostream &O) {
544  const MCOperand &MO1 = MI->getOperand(OpNum);
545  O << "[" << getRegisterName(MO1.getReg()) << "]";
546}
547
548void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
549                                                 unsigned OpNum,
550                                                 raw_ostream &O) {
551  const MCOperand &MO = MI->getOperand(OpNum);
552  if (MO.getReg() == 0)
553    O << "!";
554  else
555    O << ", " << getRegisterName(MO.getReg());
556}
557
558void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
559                                                    unsigned OpNum,
560                                                    raw_ostream &O) {
561  const MCOperand &MO = MI->getOperand(OpNum);
562  uint32_t v = ~MO.getImm();
563  int32_t lsb = CountTrailingZeros_32(v);
564  int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
565  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
566  O << '#' << lsb << ", #" << width;
567}
568
569void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
570                                     raw_ostream &O) {
571  unsigned val = MI->getOperand(OpNum).getImm();
572  O << ARM_MB::MemBOptToString(val);
573}
574
575void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
576                                          raw_ostream &O) {
577  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
578  bool isASR = (ShiftOp & (1 << 5)) != 0;
579  unsigned Amt = ShiftOp & 0x1f;
580  if (isASR)
581    O << ", asr #" << (Amt == 0 ? 32 : Amt);
582  else if (Amt)
583    O << ", lsl #" << Amt;
584}
585
586void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
587                                         raw_ostream &O) {
588  unsigned Imm = MI->getOperand(OpNum).getImm();
589  if (Imm == 0)
590    return;
591  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
592  O << ", lsl #" << Imm;
593}
594
595void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
596                                         raw_ostream &O) {
597  unsigned Imm = MI->getOperand(OpNum).getImm();
598  // A shift amount of 32 is encoded as 0.
599  if (Imm == 0)
600    Imm = 32;
601  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
602  O << ", asr #" << Imm;
603}
604
605void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
606                                       raw_ostream &O) {
607  O << "{";
608  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
609    if (i != OpNum) O << ", ";
610    O << getRegisterName(MI->getOperand(i).getReg());
611  }
612  O << "}";
613}
614
615void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
616                                        raw_ostream &O) {
617  const MCOperand &Op = MI->getOperand(OpNum);
618  if (Op.getImm())
619    O << "be";
620  else
621    O << "le";
622}
623
624void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
625                                  raw_ostream &O) {
626  const MCOperand &Op = MI->getOperand(OpNum);
627  O << ARM_PROC::IModToString(Op.getImm());
628}
629
630void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
631                                   raw_ostream &O) {
632  const MCOperand &Op = MI->getOperand(OpNum);
633  unsigned IFlags = Op.getImm();
634  for (int i=2; i >= 0; --i)
635    if (IFlags & (1 << i))
636      O << ARM_PROC::IFlagsToString(1 << i);
637
638  if (IFlags == 0)
639    O << "none";
640}
641
642void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
643                                         raw_ostream &O) {
644  const MCOperand &Op = MI->getOperand(OpNum);
645  unsigned SpecRegRBit = Op.getImm() >> 4;
646  unsigned Mask = Op.getImm() & 0xf;
647
648  if (getAvailableFeatures() & ARM::FeatureMClass) {
649    switch (Op.getImm()) {
650    default: llvm_unreachable("Unexpected mask value!");
651    case 0: O << "apsr"; return;
652    case 1: O << "iapsr"; return;
653    case 2: O << "eapsr"; return;
654    case 3: O << "xpsr"; return;
655    case 5: O << "ipsr"; return;
656    case 6: O << "epsr"; return;
657    case 7: O << "iepsr"; return;
658    case 8: O << "msp"; return;
659    case 9: O << "psp"; return;
660    case 16: O << "primask"; return;
661    case 17: O << "basepri"; return;
662    case 18: O << "basepri_max"; return;
663    case 19: O << "faultmask"; return;
664    case 20: O << "control"; return;
665    }
666  }
667
668  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
669  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
670  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
671    O << "APSR_";
672    switch (Mask) {
673    default: llvm_unreachable("Unexpected mask value!");
674    case 4:  O << "g"; return;
675    case 8:  O << "nzcvq"; return;
676    case 12: O << "nzcvqg"; return;
677    }
678  }
679
680  if (SpecRegRBit)
681    O << "SPSR";
682  else
683    O << "CPSR";
684
685  if (Mask) {
686    O << '_';
687    if (Mask & 8) O << 'f';
688    if (Mask & 4) O << 's';
689    if (Mask & 2) O << 'x';
690    if (Mask & 1) O << 'c';
691  }
692}
693
694void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
695                                           raw_ostream &O) {
696  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
697  // Handle the undefined 15 CC value here for printing so we don't abort().
698  if ((unsigned)CC == 15)
699    O << "<und>";
700  else if (CC != ARMCC::AL)
701    O << ARMCondCodeToString(CC);
702}
703
704void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
705                                                    unsigned OpNum,
706                                                    raw_ostream &O) {
707  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
708  O << ARMCondCodeToString(CC);
709}
710
711void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
712                                              raw_ostream &O) {
713  if (MI->getOperand(OpNum).getReg()) {
714    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
715           "Expect ARM CPSR register!");
716    O << 's';
717  }
718}
719
720void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
721                                          raw_ostream &O) {
722  O << MI->getOperand(OpNum).getImm();
723}
724
725void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
726                                     raw_ostream &O) {
727  O << "p" << MI->getOperand(OpNum).getImm();
728}
729
730void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
731                                     raw_ostream &O) {
732  O << "c" << MI->getOperand(OpNum).getImm();
733}
734
735void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
736                                          raw_ostream &O) {
737  O << "{" << MI->getOperand(OpNum).getImm() << "}";
738}
739
740void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
741                                  raw_ostream &O) {
742  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
743}
744
745void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
746                                            raw_ostream &O) {
747  O << "#" << MI->getOperand(OpNum).getImm() * 4;
748}
749
750void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
751                                     raw_ostream &O) {
752  unsigned Imm = MI->getOperand(OpNum).getImm();
753  O << "#" << (Imm == 0 ? 32 : Imm);
754}
755
756void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
757                                      raw_ostream &O) {
758  // (3 - the number of trailing zeros) is the number of then / else.
759  unsigned Mask = MI->getOperand(OpNum).getImm();
760  unsigned CondBit0 = Mask >> 4 & 1;
761  unsigned NumTZ = CountTrailingZeros_32(Mask);
762  assert(NumTZ <= 3 && "Invalid IT mask!");
763  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
764    bool T = ((Mask >> Pos) & 1) == CondBit0;
765    if (T)
766      O << 't';
767    else
768      O << 'e';
769  }
770}
771
772void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
773                                                 raw_ostream &O) {
774  const MCOperand &MO1 = MI->getOperand(Op);
775  const MCOperand &MO2 = MI->getOperand(Op + 1);
776
777  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
778    printOperand(MI, Op, O);
779    return;
780  }
781
782  O << "[" << getRegisterName(MO1.getReg());
783  if (unsigned RegNum = MO2.getReg())
784    O << ", " << getRegisterName(RegNum);
785  O << "]";
786}
787
788void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
789                                                    unsigned Op,
790                                                    raw_ostream &O,
791                                                    unsigned Scale) {
792  const MCOperand &MO1 = MI->getOperand(Op);
793  const MCOperand &MO2 = MI->getOperand(Op + 1);
794
795  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
796    printOperand(MI, Op, O);
797    return;
798  }
799
800  O << "[" << getRegisterName(MO1.getReg());
801  if (unsigned ImmOffs = MO2.getImm())
802    O << ", #" << ImmOffs * Scale;
803  O << "]";
804}
805
806void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
807                                                     unsigned Op,
808                                                     raw_ostream &O) {
809  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
810}
811
812void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
813                                                     unsigned Op,
814                                                     raw_ostream &O) {
815  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
816}
817
818void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
819                                                     unsigned Op,
820                                                     raw_ostream &O) {
821  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
822}
823
824void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
825                                                 raw_ostream &O) {
826  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
827}
828
829// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
830// register with shift forms.
831// REG 0   0           - e.g. R5
832// REG IMM, SH_OPC     - e.g. R5, LSL #3
833void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
834                                      raw_ostream &O) {
835  const MCOperand &MO1 = MI->getOperand(OpNum);
836  const MCOperand &MO2 = MI->getOperand(OpNum+1);
837
838  unsigned Reg = MO1.getReg();
839  O << getRegisterName(Reg);
840
841  // Print the shift opc.
842  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
843  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
844  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
845  if (ShOpc != ARM_AM::rrx)
846    O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
847}
848
849void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
850                                               raw_ostream &O) {
851  const MCOperand &MO1 = MI->getOperand(OpNum);
852  const MCOperand &MO2 = MI->getOperand(OpNum+1);
853
854  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
855    printOperand(MI, OpNum, O);
856    return;
857  }
858
859  O << "[" << getRegisterName(MO1.getReg());
860
861  int32_t OffImm = (int32_t)MO2.getImm();
862  bool isSub = OffImm < 0;
863  // Special value for #-0. All others are normal.
864  if (OffImm == INT32_MIN)
865    OffImm = 0;
866  if (isSub)
867    O << ", #-" << -OffImm;
868  else if (OffImm > 0)
869    O << ", #" << OffImm;
870  O << "]";
871}
872
873void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
874                                                unsigned OpNum,
875                                                raw_ostream &O) {
876  const MCOperand &MO1 = MI->getOperand(OpNum);
877  const MCOperand &MO2 = MI->getOperand(OpNum+1);
878
879  O << "[" << getRegisterName(MO1.getReg());
880
881  int32_t OffImm = (int32_t)MO2.getImm();
882  // Don't print +0.
883  if (OffImm == INT32_MIN)
884    O << ", #-0";
885  else if (OffImm < 0)
886    O << ", #-" << -OffImm;
887  else if (OffImm > 0)
888    O << ", #" << OffImm;
889  O << "]";
890}
891
892void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
893                                                  unsigned OpNum,
894                                                  raw_ostream &O) {
895  const MCOperand &MO1 = MI->getOperand(OpNum);
896  const MCOperand &MO2 = MI->getOperand(OpNum+1);
897
898  if (!MO1.isReg()) {   //  For label symbolic references.
899    printOperand(MI, OpNum, O);
900    return;
901  }
902
903  O << "[" << getRegisterName(MO1.getReg());
904
905  int32_t OffImm = (int32_t)MO2.getImm() / 4;
906  // Don't print +0.
907  if (OffImm < 0)
908    O << ", #-" << -OffImm * 4;
909  else if (OffImm > 0)
910    O << ", #" << OffImm * 4;
911  O << "]";
912}
913
914void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
915                                                       unsigned OpNum,
916                                                       raw_ostream &O) {
917  const MCOperand &MO1 = MI->getOperand(OpNum);
918  const MCOperand &MO2 = MI->getOperand(OpNum+1);
919
920  O << "[" << getRegisterName(MO1.getReg());
921  if (MO2.getImm())
922    O << ", #" << MO2.getImm() * 4;
923  O << "]";
924}
925
926void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
927                                                      unsigned OpNum,
928                                                      raw_ostream &O) {
929  const MCOperand &MO1 = MI->getOperand(OpNum);
930  int32_t OffImm = (int32_t)MO1.getImm();
931  // Don't print +0.
932  if (OffImm < 0)
933    O << ", #-" << -OffImm;
934  else
935    O << ", #" << OffImm;
936}
937
938void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
939                                                        unsigned OpNum,
940                                                        raw_ostream &O) {
941  const MCOperand &MO1 = MI->getOperand(OpNum);
942  int32_t OffImm = (int32_t)MO1.getImm() / 4;
943  // Don't print +0.
944  if (OffImm != 0) {
945    O << ", ";
946    if (OffImm < 0)
947      O << "#-" << -OffImm * 4;
948    else if (OffImm > 0)
949      O << "#" << OffImm * 4;
950  }
951}
952
953void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
954                                                 unsigned OpNum,
955                                                 raw_ostream &O) {
956  const MCOperand &MO1 = MI->getOperand(OpNum);
957  const MCOperand &MO2 = MI->getOperand(OpNum+1);
958  const MCOperand &MO3 = MI->getOperand(OpNum+2);
959
960  O << "[" << getRegisterName(MO1.getReg());
961
962  assert(MO2.getReg() && "Invalid so_reg load / store address!");
963  O << ", " << getRegisterName(MO2.getReg());
964
965  unsigned ShAmt = MO3.getImm();
966  if (ShAmt) {
967    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
968    O << ", lsl #" << ShAmt;
969  }
970  O << "]";
971}
972
973void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
974                                       raw_ostream &O) {
975  const MCOperand &MO = MI->getOperand(OpNum);
976  O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
977}
978
979void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
980                                            raw_ostream &O) {
981  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
982  unsigned EltBits;
983  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
984  O << "#0x";
985  O.write_hex(Val);
986}
987
988void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
989                                            raw_ostream &O) {
990  unsigned Imm = MI->getOperand(OpNum).getImm();
991  O << "#" << Imm + 1;
992}
993
994void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
995                                        raw_ostream &O) {
996  unsigned Imm = MI->getOperand(OpNum).getImm();
997  if (Imm == 0)
998    return;
999  O << ", ror #";
1000  switch (Imm) {
1001  default: assert (0 && "illegal ror immediate!");
1002  case 1: O << "8"; break;
1003  case 2: O << "16"; break;
1004  case 3: O << "24"; break;
1005  }
1006}
1007
1008void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1009                                  raw_ostream &O) {
1010  O << "#" << 16 - MI->getOperand(OpNum).getImm();
1011}
1012
1013void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1014                                  raw_ostream &O) {
1015  O << "#" << 32 - MI->getOperand(OpNum).getImm();
1016}
1017
1018void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1019                                      raw_ostream &O) {
1020  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1021}
1022
1023void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1024                                        raw_ostream &O) {
1025  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1026}
1027
1028void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1029                                        raw_ostream &O) {
1030  // Normally, it's not safe to use register enum values directly with
1031  // addition to get the next register, but for VFP registers, the
1032  // sort order is guaranteed because they're all of the form D<n>.
1033  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1034    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "}";
1035}
1036
1037void ARMInstPrinter::printVectorListDPair(const MCInst *MI, unsigned OpNum,
1038                                          raw_ostream &O) {
1039  unsigned Reg = MI->getOperand(OpNum).getReg();
1040  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1041  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1042  O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1043}
1044
1045void ARMInstPrinter::printVectorListDPairSpaced(const MCInst *MI,
1046                                                unsigned OpNum,
1047                                                raw_ostream &O) {
1048  unsigned Reg = MI->getOperand(OpNum).getReg();
1049  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1050  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1051  O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1052}
1053
1054void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1055                                          raw_ostream &O) {
1056  // Normally, it's not safe to use register enum values directly with
1057  // addition to get the next register, but for VFP registers, the
1058  // sort order is guaranteed because they're all of the form D<n>.
1059  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1060    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1061    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1062}
1063
1064void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1065                                         raw_ostream &O) {
1066  // Normally, it's not safe to use register enum values directly with
1067  // addition to get the next register, but for VFP registers, the
1068  // sort order is guaranteed because they're all of the form D<n>.
1069  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1070    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1071    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1072    << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1073}
1074
1075void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1076                                                unsigned OpNum,
1077                                                raw_ostream &O) {
1078  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1079}
1080
1081void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1082                                                unsigned OpNum,
1083                                                raw_ostream &O) {
1084  // Normally, it's not safe to use register enum values directly with
1085  // addition to get the next register, but for VFP registers, the
1086  // sort order is guaranteed because they're all of the form D<n>.
1087  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1088    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
1089}
1090
1091void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1092                                                  unsigned OpNum,
1093                                                  raw_ostream &O) {
1094  // Normally, it's not safe to use register enum values directly with
1095  // addition to get the next register, but for VFP registers, the
1096  // sort order is guaranteed because they're all of the form D<n>.
1097  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1098    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1099    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1100}
1101
1102void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1103                                                  unsigned OpNum,
1104                                                  raw_ostream &O) {
1105  // Normally, it's not safe to use register enum values directly with
1106  // addition to get the next register, but for VFP registers, the
1107  // sort order is guaranteed because they're all of the form D<n>.
1108  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1109    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1110    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1111    << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
1112}
1113
1114void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1115                                              raw_ostream &O) {
1116  // Normally, it's not safe to use register enum values directly with
1117  // addition to get the next register, but for VFP registers, the
1118  // sort order is guaranteed because they're all of the form D<n>.
1119  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1120    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1121}
1122
1123void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1124                                                      unsigned OpNum,
1125                                                      raw_ostream &O) {
1126  // Normally, it's not safe to use register enum values directly with
1127  // addition to get the next register, but for VFP registers, the
1128  // sort order is guaranteed because they're all of the form D<n>.
1129  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1130    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1131}
1132
1133void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1134                                                        unsigned OpNum,
1135                                                        raw_ostream &O) {
1136  // Normally, it's not safe to use register enum values directly with
1137  // addition to get the next register, but for VFP registers, the
1138  // sort order is guaranteed because they're all of the form D<n>.
1139  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1140    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1141    << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
1142}
1143
1144void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1145                                                       unsigned OpNum,
1146                                                       raw_ostream &O) {
1147  // Normally, it's not safe to use register enum values directly with
1148  // addition to get the next register, but for VFP registers, the
1149  // sort order is guaranteed because they're all of the form D<n>.
1150  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1151    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1152    << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
1153    << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
1154}
1155
1156void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1157                                                unsigned OpNum,
1158                                                raw_ostream &O) {
1159  // Normally, it's not safe to use register enum values directly with
1160  // addition to get the next register, but for VFP registers, the
1161  // sort order is guaranteed because they're all of the form D<n>.
1162  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1163    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1164    << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
1165}
1166
1167void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1168                                                unsigned OpNum,
1169                                                raw_ostream &O) {
1170  // Normally, it's not safe to use register enum values directly with
1171  // addition to get the next register, but for VFP registers, the
1172  // sort order is guaranteed because they're all of the form D<n>.
1173  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1174    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1175    << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
1176    << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";
1177}
1178