ARMInstPrinter.cpp revision c387fc66bd52e4276fdc2704a3aaed57cc1f9a11 
1//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an ARM MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "asm-printer"
15#include "ARMInstPrinter.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "MCTargetDesc/ARMAddressingModes.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/Support/raw_ostream.h"
22using namespace llvm;
23
24#define GET_INSTRUCTION_NAME
25#include "ARMGenAsmWriter.inc"
26
27/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
28///
29/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
30static unsigned translateShiftImm(unsigned imm) {
31  if (imm == 0)
32    return 32;
33  return imm;
34}
35
36
37ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
38                               const MCSubtargetInfo &STI) :
39  MCInstPrinter(MAI) {
40  // Initialize the set of available features.
41  setAvailableFeatures(STI.getFeatureBits());
42}
43
44StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
45  return getInstructionName(Opcode);
46}
47
48void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
49  OS << getRegisterName(RegNo);
50}
51
52void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
53                               StringRef Annot) {
54  unsigned Opcode = MI->getOpcode();
55
56  // Check for MOVs and print canonical forms, instead.
57  if (Opcode == ARM::MOVsr) {
58    // FIXME: Thumb variants?
59    const MCOperand &Dst = MI->getOperand(0);
60    const MCOperand &MO1 = MI->getOperand(1);
61    const MCOperand &MO2 = MI->getOperand(2);
62    const MCOperand &MO3 = MI->getOperand(3);
63
64    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
65    printSBitModifierOperand(MI, 6, O);
66    printPredicateOperand(MI, 4, O);
67
68    O << '\t' << getRegisterName(Dst.getReg())
69      << ", " << getRegisterName(MO1.getReg());
70
71    O << ", " << getRegisterName(MO2.getReg());
72    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
73    printAnnotation(O, Annot);
74    return;
75  }
76
77  if (Opcode == ARM::MOVsi) {
78    // FIXME: Thumb variants?
79    const MCOperand &Dst = MI->getOperand(0);
80    const MCOperand &MO1 = MI->getOperand(1);
81    const MCOperand &MO2 = MI->getOperand(2);
82
83    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
84    printSBitModifierOperand(MI, 5, O);
85    printPredicateOperand(MI, 3, O);
86
87    O << '\t' << getRegisterName(Dst.getReg())
88      << ", " << getRegisterName(MO1.getReg());
89
90    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
91      printAnnotation(O, Annot);
92      return;
93    }
94
95    O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
96    printAnnotation(O, Annot);
97    return;
98  }
99
100
101  // A8.6.123 PUSH
102  if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
103      MI->getOperand(0).getReg() == ARM::SP &&
104      MI->getNumOperands() > 5) {
105    // Should only print PUSH if there are at least two registers in the list.
106    O << '\t' << "push";
107    printPredicateOperand(MI, 2, O);
108    if (Opcode == ARM::t2STMDB_UPD)
109      O << ".w";
110    O << '\t';
111    printRegisterList(MI, 4, O);
112    printAnnotation(O, Annot);
113    return;
114  }
115  if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
116      MI->getOperand(3).getImm() == -4) {
117    O << '\t' << "push";
118    printPredicateOperand(MI, 4, O);
119    O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
120    printAnnotation(O, Annot);
121    return;
122  }
123
124  // A8.6.122 POP
125  if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
126      MI->getOperand(0).getReg() == ARM::SP &&
127      MI->getNumOperands() > 5) {
128    // Should only print POP if there are at least two registers in the list.
129    O << '\t' << "pop";
130    printPredicateOperand(MI, 2, O);
131    if (Opcode == ARM::t2LDMIA_UPD)
132      O << ".w";
133    O << '\t';
134    printRegisterList(MI, 4, O);
135    printAnnotation(O, Annot);
136    return;
137  }
138  if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
139      MI->getOperand(4).getImm() == 4) {
140    O << '\t' << "pop";
141    printPredicateOperand(MI, 5, O);
142    O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
143    printAnnotation(O, Annot);
144    return;
145  }
146
147
148  // A8.6.355 VPUSH
149  if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
150      MI->getOperand(0).getReg() == ARM::SP) {
151    O << '\t' << "vpush";
152    printPredicateOperand(MI, 2, O);
153    O << '\t';
154    printRegisterList(MI, 4, O);
155    printAnnotation(O, Annot);
156    return;
157  }
158
159  // A8.6.354 VPOP
160  if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
161      MI->getOperand(0).getReg() == ARM::SP) {
162    O << '\t' << "vpop";
163    printPredicateOperand(MI, 2, O);
164    O << '\t';
165    printRegisterList(MI, 4, O);
166    printAnnotation(O, Annot);
167    return;
168  }
169
170  if (Opcode == ARM::tLDMIA) {
171    bool Writeback = true;
172    unsigned BaseReg = MI->getOperand(0).getReg();
173    for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
174      if (MI->getOperand(i).getReg() == BaseReg)
175        Writeback = false;
176    }
177
178    O << "\tldm";
179
180    printPredicateOperand(MI, 1, O);
181    O << '\t' << getRegisterName(BaseReg);
182    if (Writeback) O << "!";
183    O << ", ";
184    printRegisterList(MI, 3, O);
185    printAnnotation(O, Annot);
186    return;
187  }
188
189  // Thumb1 NOP
190  if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
191      MI->getOperand(1).getReg() == ARM::R8) {
192    O << "\tnop";
193    printPredicateOperand(MI, 2, O);
194    printAnnotation(O, Annot);
195    return;
196  }
197
198  printInstruction(MI, O);
199  printAnnotation(O, Annot);
200}
201
202void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
203                                  raw_ostream &O) {
204  const MCOperand &Op = MI->getOperand(OpNo);
205  if (Op.isReg()) {
206    unsigned Reg = Op.getReg();
207    O << getRegisterName(Reg);
208  } else if (Op.isImm()) {
209    O << '#' << Op.getImm();
210  } else {
211    assert(Op.isExpr() && "unknown operand kind in printOperand");
212    // If a symbolic branch target was added as a constant expression then print
213    // that address in hex.
214    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
215    int64_t Address;
216    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
217      O << "0x";
218      O.write_hex(Address);
219    }
220    else {
221      // Otherwise, just print the expression.
222      O << *Op.getExpr();
223    }
224  }
225}
226
227void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
228                                       raw_ostream &O) {
229  const MCOperand &MO1 = MI->getOperand(OpNum);
230  if (MO1.isExpr())
231    O << *MO1.getExpr();
232  else if (MO1.isImm())
233    O << "[pc, #" << MO1.getImm() << "]";
234  else
235    llvm_unreachable("Unknown LDR label operand?");
236}
237
238// so_reg is a 4-operand unit corresponding to register forms of the A5.1
239// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
240//    REG 0   0           - e.g. R5
241//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
242//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
243void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
244                                       raw_ostream &O) {
245  const MCOperand &MO1 = MI->getOperand(OpNum);
246  const MCOperand &MO2 = MI->getOperand(OpNum+1);
247  const MCOperand &MO3 = MI->getOperand(OpNum+2);
248
249  O << getRegisterName(MO1.getReg());
250
251  // Print the shift opc.
252  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
253  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
254  if (ShOpc == ARM_AM::rrx)
255    return;
256
257  O << ' ' << getRegisterName(MO2.getReg());
258  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
259}
260
261void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
262                                       raw_ostream &O) {
263  const MCOperand &MO1 = MI->getOperand(OpNum);
264  const MCOperand &MO2 = MI->getOperand(OpNum+1);
265
266  O << getRegisterName(MO1.getReg());
267
268  // Print the shift opc.
269  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
270  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
271  if (ShOpc == ARM_AM::rrx)
272    return;
273  O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
274}
275
276
277//===--------------------------------------------------------------------===//
278// Addressing Mode #2
279//===--------------------------------------------------------------------===//
280
281void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
282                                                raw_ostream &O) {
283  const MCOperand &MO1 = MI->getOperand(Op);
284  const MCOperand &MO2 = MI->getOperand(Op+1);
285  const MCOperand &MO3 = MI->getOperand(Op+2);
286
287  O << "[" << getRegisterName(MO1.getReg());
288
289  if (!MO2.getReg()) {
290    if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
291      O << ", #"
292        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
293        << ARM_AM::getAM2Offset(MO3.getImm());
294    O << "]";
295    return;
296  }
297
298  O << ", "
299    << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
300    << getRegisterName(MO2.getReg());
301
302  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
303    O << ", "
304    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
305    << " #" << ShImm;
306  O << "]";
307}
308
309void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
310                                         raw_ostream &O) {
311  const MCOperand &MO1 = MI->getOperand(Op);
312  const MCOperand &MO2 = MI->getOperand(Op+1);
313  const MCOperand &MO3 = MI->getOperand(Op+2);
314
315  O << "[" << getRegisterName(MO1.getReg()) << "], ";
316
317  if (!MO2.getReg()) {
318    unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
319    O << '#'
320      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
321      << ImmOffs;
322    return;
323  }
324
325  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
326    << getRegisterName(MO2.getReg());
327
328  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
329    O << ", "
330    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
331    << " #" << ShImm;
332}
333
334void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
335                                           raw_ostream &O) {
336  const MCOperand &MO1 = MI->getOperand(Op);
337  const MCOperand &MO2 = MI->getOperand(Op+1);
338  O << "[" << getRegisterName(MO1.getReg()) << ", "
339    << getRegisterName(MO2.getReg()) << "]";
340}
341
342void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
343                                           raw_ostream &O) {
344  const MCOperand &MO1 = MI->getOperand(Op);
345  const MCOperand &MO2 = MI->getOperand(Op+1);
346  O << "[" << getRegisterName(MO1.getReg()) << ", "
347    << getRegisterName(MO2.getReg()) << ", lsl #1]";
348}
349
350void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
351                                           raw_ostream &O) {
352  const MCOperand &MO1 = MI->getOperand(Op);
353
354  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
355    printOperand(MI, Op, O);
356    return;
357  }
358
359  const MCOperand &MO3 = MI->getOperand(Op+2);
360  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
361
362  if (IdxMode == ARMII::IndexModePost) {
363    printAM2PostIndexOp(MI, Op, O);
364    return;
365  }
366  printAM2PreOrOffsetIndexOp(MI, Op, O);
367}
368
369void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
370                                                 unsigned OpNum,
371                                                 raw_ostream &O) {
372  const MCOperand &MO1 = MI->getOperand(OpNum);
373  const MCOperand &MO2 = MI->getOperand(OpNum+1);
374
375  if (!MO1.getReg()) {
376    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
377    O << '#'
378      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
379      << ImmOffs;
380    return;
381  }
382
383  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
384    << getRegisterName(MO1.getReg());
385
386  if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
387    O << ", "
388    << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
389    << " #" << ShImm;
390}
391
392//===--------------------------------------------------------------------===//
393// Addressing Mode #3
394//===--------------------------------------------------------------------===//
395
396void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
397                                         raw_ostream &O) {
398  const MCOperand &MO1 = MI->getOperand(Op);
399  const MCOperand &MO2 = MI->getOperand(Op+1);
400  const MCOperand &MO3 = MI->getOperand(Op+2);
401
402  O << "[" << getRegisterName(MO1.getReg()) << "], ";
403
404  if (MO2.getReg()) {
405    O << (char)ARM_AM::getAM3Op(MO3.getImm())
406    << getRegisterName(MO2.getReg());
407    return;
408  }
409
410  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
411  O << '#'
412    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
413    << ImmOffs;
414}
415
416void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
417                                                raw_ostream &O) {
418  const MCOperand &MO1 = MI->getOperand(Op);
419  const MCOperand &MO2 = MI->getOperand(Op+1);
420  const MCOperand &MO3 = MI->getOperand(Op+2);
421
422  O << '[' << getRegisterName(MO1.getReg());
423
424  if (MO2.getReg()) {
425    O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
426      << getRegisterName(MO2.getReg()) << ']';
427    return;
428  }
429
430  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
431    O << ", #"
432      << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
433      << ImmOffs;
434  O << ']';
435}
436
437void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
438                                           raw_ostream &O) {
439  const MCOperand &MO1 = MI->getOperand(Op);
440  if (!MO1.isReg()) {   //  For label symbolic references.
441    printOperand(MI, Op, O);
442    return;
443  }
444
445  const MCOperand &MO3 = MI->getOperand(Op+2);
446  unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
447
448  if (IdxMode == ARMII::IndexModePost) {
449    printAM3PostIndexOp(MI, Op, O);
450    return;
451  }
452  printAM3PreOrOffsetIndexOp(MI, Op, O);
453}
454
455void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
456                                                 unsigned OpNum,
457                                                 raw_ostream &O) {
458  const MCOperand &MO1 = MI->getOperand(OpNum);
459  const MCOperand &MO2 = MI->getOperand(OpNum+1);
460
461  if (MO1.getReg()) {
462    O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
463      << getRegisterName(MO1.getReg());
464    return;
465  }
466
467  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
468  O << '#'
469    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
470    << ImmOffs;
471}
472
473void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
474                                             unsigned OpNum,
475                                             raw_ostream &O) {
476  const MCOperand &MO = MI->getOperand(OpNum);
477  unsigned Imm = MO.getImm();
478  O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
479}
480
481void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
482                                            raw_ostream &O) {
483  const MCOperand &MO1 = MI->getOperand(OpNum);
484  const MCOperand &MO2 = MI->getOperand(OpNum+1);
485
486  O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
487}
488
489void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
490                                             unsigned OpNum,
491                                             raw_ostream &O) {
492  const MCOperand &MO = MI->getOperand(OpNum);
493  unsigned Imm = MO.getImm();
494  O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
495}
496
497
498void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
499                                           raw_ostream &O) {
500  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
501                                                 .getImm());
502  O << ARM_AM::getAMSubModeStr(Mode);
503}
504
505void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
506                                           raw_ostream &O) {
507  const MCOperand &MO1 = MI->getOperand(OpNum);
508  const MCOperand &MO2 = MI->getOperand(OpNum+1);
509
510  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
511    printOperand(MI, OpNum, O);
512    return;
513  }
514
515  O << "[" << getRegisterName(MO1.getReg());
516
517  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
518  unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
519  if (ImmOffs || Op == ARM_AM::sub) {
520    O << ", #"
521      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
522      << ImmOffs * 4;
523  }
524  O << "]";
525}
526
527void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
528                                           raw_ostream &O) {
529  const MCOperand &MO1 = MI->getOperand(OpNum);
530  const MCOperand &MO2 = MI->getOperand(OpNum+1);
531
532  O << "[" << getRegisterName(MO1.getReg());
533  if (MO2.getImm()) {
534    // FIXME: Both darwin as and GNU as violate ARM docs here.
535    O << ", :" << (MO2.getImm() << 3);
536  }
537  O << "]";
538}
539
540void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
541                                           raw_ostream &O) {
542  const MCOperand &MO1 = MI->getOperand(OpNum);
543  O << "[" << getRegisterName(MO1.getReg()) << "]";
544}
545
546void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
547                                                 unsigned OpNum,
548                                                 raw_ostream &O) {
549  const MCOperand &MO = MI->getOperand(OpNum);
550  if (MO.getReg() == 0)
551    O << "!";
552  else
553    O << ", " << getRegisterName(MO.getReg());
554}
555
556void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
557                                                    unsigned OpNum,
558                                                    raw_ostream &O) {
559  const MCOperand &MO = MI->getOperand(OpNum);
560  uint32_t v = ~MO.getImm();
561  int32_t lsb = CountTrailingZeros_32(v);
562  int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
563  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
564  O << '#' << lsb << ", #" << width;
565}
566
567void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
568                                     raw_ostream &O) {
569  unsigned val = MI->getOperand(OpNum).getImm();
570  O << ARM_MB::MemBOptToString(val);
571}
572
573void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
574                                          raw_ostream &O) {
575  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
576  bool isASR = (ShiftOp & (1 << 5)) != 0;
577  unsigned Amt = ShiftOp & 0x1f;
578  if (isASR)
579    O << ", asr #" << (Amt == 0 ? 32 : Amt);
580  else if (Amt)
581    O << ", lsl #" << Amt;
582}
583
584void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
585                                         raw_ostream &O) {
586  unsigned Imm = MI->getOperand(OpNum).getImm();
587  if (Imm == 0)
588    return;
589  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
590  O << ", lsl #" << Imm;
591}
592
593void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
594                                         raw_ostream &O) {
595  unsigned Imm = MI->getOperand(OpNum).getImm();
596  // A shift amount of 32 is encoded as 0.
597  if (Imm == 0)
598    Imm = 32;
599  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
600  O << ", asr #" << Imm;
601}
602
603void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
604                                       raw_ostream &O) {
605  O << "{";
606  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
607    if (i != OpNum) O << ", ";
608    O << getRegisterName(MI->getOperand(i).getReg());
609  }
610  O << "}";
611}
612
613void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
614                                        raw_ostream &O) {
615  const MCOperand &Op = MI->getOperand(OpNum);
616  if (Op.getImm())
617    O << "be";
618  else
619    O << "le";
620}
621
622void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
623                                  raw_ostream &O) {
624  const MCOperand &Op = MI->getOperand(OpNum);
625  O << ARM_PROC::IModToString(Op.getImm());
626}
627
628void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
629                                   raw_ostream &O) {
630  const MCOperand &Op = MI->getOperand(OpNum);
631  unsigned IFlags = Op.getImm();
632  for (int i=2; i >= 0; --i)
633    if (IFlags & (1 << i))
634      O << ARM_PROC::IFlagsToString(1 << i);
635
636  if (IFlags == 0)
637    O << "none";
638}
639
640void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
641                                         raw_ostream &O) {
642  const MCOperand &Op = MI->getOperand(OpNum);
643  unsigned SpecRegRBit = Op.getImm() >> 4;
644  unsigned Mask = Op.getImm() & 0xf;
645
646  if (getAvailableFeatures() & ARM::FeatureMClass) {
647    switch (Op.getImm()) {
648    default: assert(0 && "Unexpected mask value!");
649    case 0: O << "apsr"; return;
650    case 1: O << "iapsr"; return;
651    case 2: O << "eapsr"; return;
652    case 3: O << "xpsr"; return;
653    case 5: O << "ipsr"; return;
654    case 6: O << "epsr"; return;
655    case 7: O << "iepsr"; return;
656    case 8: O << "msp"; return;
657    case 9: O << "psp"; return;
658    case 16: O << "primask"; return;
659    case 17: O << "basepri"; return;
660    case 18: O << "basepri_max"; return;
661    case 19: O << "faultmask"; return;
662    case 20: O << "control"; return;
663    }
664  }
665
666  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
667  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
668  if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
669    O << "APSR_";
670    switch (Mask) {
671    default: assert(0);
672    case 4:  O << "g"; return;
673    case 8:  O << "nzcvq"; return;
674    case 12: O << "nzcvqg"; return;
675    }
676    llvm_unreachable("Unexpected mask value!");
677  }
678
679  if (SpecRegRBit)
680    O << "SPSR";
681  else
682    O << "CPSR";
683
684  if (Mask) {
685    O << '_';
686    if (Mask & 8) O << 'f';
687    if (Mask & 4) O << 's';
688    if (Mask & 2) O << 'x';
689    if (Mask & 1) O << 'c';
690  }
691}
692
693void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
694                                           raw_ostream &O) {
695  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
696  if (CC != ARMCC::AL)
697    O << ARMCondCodeToString(CC);
698}
699
700void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
701                                                    unsigned OpNum,
702                                                    raw_ostream &O) {
703  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
704  O << ARMCondCodeToString(CC);
705}
706
707void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
708                                              raw_ostream &O) {
709  if (MI->getOperand(OpNum).getReg()) {
710    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
711           "Expect ARM CPSR register!");
712    O << 's';
713  }
714}
715
716void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
717                                          raw_ostream &O) {
718  O << MI->getOperand(OpNum).getImm();
719}
720
721void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
722                                     raw_ostream &O) {
723  O << "p" << MI->getOperand(OpNum).getImm();
724}
725
726void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
727                                     raw_ostream &O) {
728  O << "c" << MI->getOperand(OpNum).getImm();
729}
730
731void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
732                                          raw_ostream &O) {
733  O << "{" << MI->getOperand(OpNum).getImm() << "}";
734}
735
736void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
737                                  raw_ostream &O) {
738  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
739}
740
741void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
742                                            raw_ostream &O) {
743  O << "#" << MI->getOperand(OpNum).getImm() * 4;
744}
745
746void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
747                                     raw_ostream &O) {
748  unsigned Imm = MI->getOperand(OpNum).getImm();
749  O << "#" << (Imm == 0 ? 32 : Imm);
750}
751
752void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
753                                      raw_ostream &O) {
754  // (3 - the number of trailing zeros) is the number of then / else.
755  unsigned Mask = MI->getOperand(OpNum).getImm();
756  unsigned CondBit0 = Mask >> 4 & 1;
757  unsigned NumTZ = CountTrailingZeros_32(Mask);
758  assert(NumTZ <= 3 && "Invalid IT mask!");
759  for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
760    bool T = ((Mask >> Pos) & 1) == CondBit0;
761    if (T)
762      O << 't';
763    else
764      O << 'e';
765  }
766}
767
768void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
769                                                 raw_ostream &O) {
770  const MCOperand &MO1 = MI->getOperand(Op);
771  const MCOperand &MO2 = MI->getOperand(Op + 1);
772
773  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
774    printOperand(MI, Op, O);
775    return;
776  }
777
778  O << "[" << getRegisterName(MO1.getReg());
779  if (unsigned RegNum = MO2.getReg())
780    O << ", " << getRegisterName(RegNum);
781  O << "]";
782}
783
784void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
785                                                    unsigned Op,
786                                                    raw_ostream &O,
787                                                    unsigned Scale) {
788  const MCOperand &MO1 = MI->getOperand(Op);
789  const MCOperand &MO2 = MI->getOperand(Op + 1);
790
791  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
792    printOperand(MI, Op, O);
793    return;
794  }
795
796  O << "[" << getRegisterName(MO1.getReg());
797  if (unsigned ImmOffs = MO2.getImm())
798    O << ", #" << ImmOffs * Scale;
799  O << "]";
800}
801
802void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
803                                                     unsigned Op,
804                                                     raw_ostream &O) {
805  printThumbAddrModeImm5SOperand(MI, Op, O, 1);
806}
807
808void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
809                                                     unsigned Op,
810                                                     raw_ostream &O) {
811  printThumbAddrModeImm5SOperand(MI, Op, O, 2);
812}
813
814void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
815                                                     unsigned Op,
816                                                     raw_ostream &O) {
817  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
818}
819
820void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
821                                                 raw_ostream &O) {
822  printThumbAddrModeImm5SOperand(MI, Op, O, 4);
823}
824
825// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
826// register with shift forms.
827// REG 0   0           - e.g. R5
828// REG IMM, SH_OPC     - e.g. R5, LSL #3
829void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
830                                      raw_ostream &O) {
831  const MCOperand &MO1 = MI->getOperand(OpNum);
832  const MCOperand &MO2 = MI->getOperand(OpNum+1);
833
834  unsigned Reg = MO1.getReg();
835  O << getRegisterName(Reg);
836
837  // Print the shift opc.
838  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
839  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
840  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
841  if (ShOpc != ARM_AM::rrx)
842    O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
843}
844
845void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
846                                               raw_ostream &O) {
847  const MCOperand &MO1 = MI->getOperand(OpNum);
848  const MCOperand &MO2 = MI->getOperand(OpNum+1);
849
850  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
851    printOperand(MI, OpNum, O);
852    return;
853  }
854
855  O << "[" << getRegisterName(MO1.getReg());
856
857  int32_t OffImm = (int32_t)MO2.getImm();
858  bool isSub = OffImm < 0;
859  // Special value for #-0. All others are normal.
860  if (OffImm == INT32_MIN)
861    OffImm = 0;
862  if (isSub)
863    O << ", #-" << -OffImm;
864  else if (OffImm > 0)
865    O << ", #" << OffImm;
866  O << "]";
867}
868
869void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
870                                                unsigned OpNum,
871                                                raw_ostream &O) {
872  const MCOperand &MO1 = MI->getOperand(OpNum);
873  const MCOperand &MO2 = MI->getOperand(OpNum+1);
874
875  O << "[" << getRegisterName(MO1.getReg());
876
877  int32_t OffImm = (int32_t)MO2.getImm();
878  // Don't print +0.
879  if (OffImm == INT32_MIN)
880    O << ", #-0";
881  else if (OffImm < 0)
882    O << ", #-" << -OffImm;
883  else if (OffImm > 0)
884    O << ", #" << OffImm;
885  O << "]";
886}
887
888void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
889                                                  unsigned OpNum,
890                                                  raw_ostream &O) {
891  const MCOperand &MO1 = MI->getOperand(OpNum);
892  const MCOperand &MO2 = MI->getOperand(OpNum+1);
893
894  if (!MO1.isReg()) {   //  For label symbolic references.
895    printOperand(MI, OpNum, O);
896    return;
897  }
898
899  O << "[" << getRegisterName(MO1.getReg());
900
901  int32_t OffImm = (int32_t)MO2.getImm() / 4;
902  // Don't print +0.
903  if (OffImm < 0)
904    O << ", #-" << -OffImm * 4;
905  else if (OffImm > 0)
906    O << ", #" << OffImm * 4;
907  O << "]";
908}
909
910void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
911                                                       unsigned OpNum,
912                                                       raw_ostream &O) {
913  const MCOperand &MO1 = MI->getOperand(OpNum);
914  const MCOperand &MO2 = MI->getOperand(OpNum+1);
915
916  O << "[" << getRegisterName(MO1.getReg());
917  if (MO2.getImm())
918    O << ", #" << MO2.getImm() * 4;
919  O << "]";
920}
921
922void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
923                                                      unsigned OpNum,
924                                                      raw_ostream &O) {
925  const MCOperand &MO1 = MI->getOperand(OpNum);
926  int32_t OffImm = (int32_t)MO1.getImm();
927  // Don't print +0.
928  if (OffImm < 0)
929    O << ", #-" << -OffImm;
930  else
931    O << ", #" << OffImm;
932}
933
934void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
935                                                        unsigned OpNum,
936                                                        raw_ostream &O) {
937  const MCOperand &MO1 = MI->getOperand(OpNum);
938  int32_t OffImm = (int32_t)MO1.getImm() / 4;
939  // Don't print +0.
940  if (OffImm != 0) {
941    O << ", ";
942    if (OffImm < 0)
943      O << "#-" << -OffImm * 4;
944    else if (OffImm > 0)
945      O << "#" << OffImm * 4;
946  }
947}
948
949void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
950                                                 unsigned OpNum,
951                                                 raw_ostream &O) {
952  const MCOperand &MO1 = MI->getOperand(OpNum);
953  const MCOperand &MO2 = MI->getOperand(OpNum+1);
954  const MCOperand &MO3 = MI->getOperand(OpNum+2);
955
956  O << "[" << getRegisterName(MO1.getReg());
957
958  assert(MO2.getReg() && "Invalid so_reg load / store address!");
959  O << ", " << getRegisterName(MO2.getReg());
960
961  unsigned ShAmt = MO3.getImm();
962  if (ShAmt) {
963    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
964    O << ", lsl #" << ShAmt;
965  }
966  O << "]";
967}
968
969void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
970                                       raw_ostream &O) {
971  const MCOperand &MO = MI->getOperand(OpNum);
972  O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
973}
974
975void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
976                                            raw_ostream &O) {
977  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
978  unsigned EltBits;
979  uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
980  O << "#0x";
981  O.write_hex(Val);
982}
983
984void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
985                                            raw_ostream &O) {
986  unsigned Imm = MI->getOperand(OpNum).getImm();
987  O << "#" << Imm + 1;
988}
989
990void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
991                                        raw_ostream &O) {
992  unsigned Imm = MI->getOperand(OpNum).getImm();
993  if (Imm == 0)
994    return;
995  O << ", ror #";
996  switch (Imm) {
997  default: assert (0 && "illegal ror immediate!");
998  case 1: O << "8"; break;
999  case 2: O << "16"; break;
1000  case 3: O << "24"; break;
1001  }
1002}
1003
1004void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1005                                  raw_ostream &O) {
1006  O << "#" << 16 - MI->getOperand(OpNum).getImm();
1007}
1008
1009void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1010                                  raw_ostream &O) {
1011  O << "#" << 32 - MI->getOperand(OpNum).getImm();
1012}
1013
1014void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1015                                      raw_ostream &O) {
1016  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1017}
1018
1019void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1020                                        raw_ostream &O) {
1021  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1022}
1023
1024void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1025                                        raw_ostream &O) {
1026  // Normally, it's not safe to use register enum values directly with
1027  // addition to get the next register, but for VFP registers, the
1028  // sort order is guaranteed because they're all of the form D<n>.
1029  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1030    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "}";
1031}
1032
1033void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1034                                          raw_ostream &O) {
1035  // Normally, it's not safe to use register enum values directly with
1036  // addition to get the next register, but for VFP registers, the
1037  // sort order is guaranteed because they're all of the form D<n>.
1038  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1039    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1040    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1041}
1042
1043void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1044                                         raw_ostream &O) {
1045  // Normally, it's not safe to use register enum values directly with
1046  // addition to get the next register, but for VFP registers, the
1047  // sort order is guaranteed because they're all of the form D<n>.
1048  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1049    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1050    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1051    << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1052}
1053
1054void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1055                                                unsigned OpNum,
1056                                                raw_ostream &O) {
1057  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1058}
1059
1060void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1061                                                unsigned OpNum,
1062                                                raw_ostream &O) {
1063  // Normally, it's not safe to use register enum values directly with
1064  // addition to get the next register, but for VFP registers, the
1065  // sort order is guaranteed because they're all of the form D<n>.
1066  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1067    << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
1068}
1069
1070void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1071                                              raw_ostream &O) {
1072  // Normally, it's not safe to use register enum values directly with
1073  // addition to get the next register, but for VFP registers, the
1074  // sort order is guaranteed because they're all of the form D<n>.
1075  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1076    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1077}
1078
1079void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1080                                                      unsigned OpNum,
1081                                                      raw_ostream &O) {
1082  // Normally, it's not safe to use register enum values directly with
1083  // addition to get the next register, but for VFP registers, the
1084  // sort order is guaranteed because they're all of the form D<n>.
1085  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1086    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1087}
1088
1089void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1090                                                unsigned OpNum,
1091                                                raw_ostream &O) {
1092  // Normally, it's not safe to use register enum values directly with
1093  // addition to get the next register, but for VFP registers, the
1094  // sort order is guaranteed because they're all of the form D<n>.
1095  O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1096    << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1097    << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
1098}
1099