MipsInstrInfo.h revision c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 
1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSINSTRUCTIONINFO_H
15#define MIPSINSTRUCTIONINFO_H
16
17#include "Mips.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "MipsRegisterInfo.h"
20
21namespace llvm {
22
23namespace Mips {
24
25  // Mips Condition Codes
26  enum CondCode {
27    COND_E,
28    COND_GZ,
29    COND_GEZ,
30    COND_LZ,
31    COND_LEZ,
32    COND_NE,
33    COND_INVALID
34  };
35
36  // Turn condition code into conditional branch opcode.
37  unsigned GetCondBranchFromCond(CondCode CC);
38
39  /// GetOppositeBranchCondition - Return the inverse of the specified cond,
40  /// e.g. turning COND_E to COND_NE.
41  CondCode GetOppositeBranchCondition(Mips::CondCode CC);
42
43}
44
45class MipsInstrInfo : public TargetInstrInfoImpl {
46  MipsTargetMachine &TM;
47  const MipsRegisterInfo RI;
48public:
49  explicit MipsInstrInfo(MipsTargetMachine &TM);
50
51  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
52  /// such, whenever a client has an instance of instruction info, it should
53  /// always be able to get register info as well (through this method).
54  ///
55  virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
56
57  /// Return true if the instruction is a register to register move and
58  /// leave the source and dest operands in the passed parameters.
59  ///
60  virtual bool isMoveInstr(const MachineInstr &MI,
61                           unsigned &SrcReg, unsigned &DstReg) const;
62
63  /// isLoadFromStackSlot - If the specified machine instruction is a direct
64  /// load from a stack slot, return the virtual or physical register number of
65  /// the destination along with the FrameIndex of the loaded stack slot.  If
66  /// not, return 0.  This predicate must return 0 if the instruction has
67  /// any side effects other than loading from the stack slot.
68  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
69
70  /// isStoreToStackSlot - If the specified machine instruction is a direct
71  /// store to a stack slot, return the virtual or physical register number of
72  /// the source reg along with the FrameIndex of the loaded stack slot.  If
73  /// not, return 0.  This predicate must return 0 if the instruction has
74  /// any side effects other than storing to the stack slot.
75  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
76
77  /// Branch Analysis
78  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
79                             MachineBasicBlock *&FBB,
80                             std::vector<MachineOperand> &Cond) const;
81  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
82  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
83                                MachineBasicBlock *FBB,
84                                const std::vector<MachineOperand> &Cond) const;
85  virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
86                            unsigned DestReg, unsigned SrcReg,
87                            const TargetRegisterClass *DestRC,
88                            const TargetRegisterClass *SrcRC) const;
89  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
90                                   MachineBasicBlock::iterator MBBI,
91                                   unsigned SrcReg, bool isKill, int FrameIndex,
92                                   const TargetRegisterClass *RC) const;
93
94  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
95                              SmallVectorImpl<MachineOperand> &Addr,
96                              const TargetRegisterClass *RC,
97                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
98
99  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
100                                    MachineBasicBlock::iterator MBBI,
101                                    unsigned DestReg, int FrameIndex,
102                                    const TargetRegisterClass *RC) const;
103
104  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
105                               SmallVectorImpl<MachineOperand> &Addr,
106                               const TargetRegisterClass *RC,
107                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
108
109  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
110                                          MachineInstr* MI,
111                                          SmallVectorImpl<unsigned> &Ops,
112                                          int FrameIndex) const;
113
114  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
115                                          MachineInstr* MI,
116                                          SmallVectorImpl<unsigned> &Ops,
117                                          MachineInstr* LoadMI) const {
118    return 0;
119  }
120
121  virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
122  virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
123
124  /// Insert nop instruction when hazard condition is found
125  virtual void insertNoop(MachineBasicBlock &MBB,
126                          MachineBasicBlock::iterator MI) const;
127};
128
129}
130
131#endif
132