MipsInstrInfo.h revision d4b48b283c3939962f0cd3c17aedc40209d82b1a 
1//===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSINSTRUCTIONINFO_H
15#define MIPSINSTRUCTIONINFO_H
16
17#include "Mips.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsRegisterInfo.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "llvm/Target/TargetInstrInfo.h"
22
23#define GET_INSTRINFO_HEADER
24#include "MipsGenInstrInfo.inc"
25
26namespace llvm {
27
28class MipsInstrInfo : public MipsGenInstrInfo {
29  MipsTargetMachine &TM;
30  bool IsN64;
31  const MipsRegisterInfo RI;
32  unsigned UncondBrOpc;
33public:
34  explicit MipsInstrInfo(MipsTargetMachine &TM);
35
36  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
37  /// such, whenever a client has an instance of instruction info, it should
38  /// always be able to get register info as well (through this method).
39  ///
40  virtual const MipsRegisterInfo &getRegisterInfo() const;
41
42  /// isLoadFromStackSlot - If the specified machine instruction is a direct
43  /// load from a stack slot, return the virtual or physical register number of
44  /// the destination along with the FrameIndex of the loaded stack slot.  If
45  /// not, return 0.  This predicate must return 0 if the instruction has
46  /// any side effects other than loading from the stack slot.
47  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
48                                       int &FrameIndex) const;
49
50  /// isStoreToStackSlot - If the specified machine instruction is a direct
51  /// store to a stack slot, return the virtual or physical register number of
52  /// the source reg along with the FrameIndex of the loaded stack slot.  If
53  /// not, return 0.  This predicate must return 0 if the instruction has
54  /// any side effects other than storing to the stack slot.
55  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
56                                      int &FrameIndex) const;
57
58  /// Branch Analysis
59  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
60                             MachineBasicBlock *&FBB,
61                             SmallVectorImpl<MachineOperand> &Cond,
62                             bool AllowModify) const;
63  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
64
65private:
66  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
67                   const SmallVectorImpl<MachineOperand>& Cond) const;
68  void ExpandExtractElementF64(MachineBasicBlock &MBB,
69                               MachineBasicBlock::iterator I) const;
70  void ExpandBuildPairF64(MachineBasicBlock &MBB,
71                          MachineBasicBlock::iterator I) const;
72
73public:
74  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
75                                MachineBasicBlock *FBB,
76                                const SmallVectorImpl<MachineOperand> &Cond,
77                                DebugLoc DL) const;
78  virtual void copyPhysReg(MachineBasicBlock &MBB,
79                           MachineBasicBlock::iterator MI, DebugLoc DL,
80                           unsigned DestReg, unsigned SrcReg,
81                           bool KillSrc) const;
82  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
83                                   MachineBasicBlock::iterator MBBI,
84                                   unsigned SrcReg, bool isKill, int FrameIndex,
85                                   const TargetRegisterClass *RC,
86                                   const TargetRegisterInfo *TRI) const;
87
88  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
89                                    MachineBasicBlock::iterator MBBI,
90                                    unsigned DestReg, int FrameIndex,
91                                    const TargetRegisterClass *RC,
92                                    const TargetRegisterInfo *TRI) const;
93
94  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
95
96  virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
97                                                 int FrameIx, uint64_t Offset,
98                                                 const MDNode *MDPtr,
99                                                 DebugLoc DL) const;
100
101  virtual
102  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
103
104  /// Insert nop instruction when hazard condition is found
105  virtual void insertNoop(MachineBasicBlock &MBB,
106                          MachineBasicBlock::iterator MI) const;
107
108  /// Return the number of bytes of code the specified instruction may be.
109  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
110};
111
112namespace Mips {
113  /// GetOppositeBranchOpc - Return the inverse of the specified
114  /// opcode, e.g. turning BEQ to BNE.
115  unsigned GetOppositeBranchOpc(unsigned Opc);
116
117  /// Emit a series of instructions to load an immediate. All instructions
118  /// except for the last one are emitted. The function returns the number of
119  /// MachineInstrs generated. The opcode-immediate pair of the last
120  /// instruction is returned in LastInst, if it is not 0.
121  unsigned
122  loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
123                MachineBasicBlock& MBB, MachineBasicBlock::iterator II,
124                DebugLoc DL, bool LastInstrIsADDiu,
125                MipsAnalyzeImmediate::Inst *LastInst);
126}
127
128}
129
130#endif
131