SubtargetEmitter.cpp revision a809c8db3d052e9b7dfaf8665ab3ce1a0b0dc859 
1//===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend emits subtarget enumerations.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "subtarget-emitter"
15
16#include "CodeGenTarget.h"
17#include "CodeGenSchedule.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringExtras.h"
20#include "llvm/MC/MCInstrItineraries.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/Format.h"
23#include "llvm/TableGen/Error.h"
24#include "llvm/TableGen/Record.h"
25#include "llvm/TableGen/TableGenBackend.h"
26#include <algorithm>
27#include <map>
28#include <string>
29#include <vector>
30using namespace llvm;
31
32namespace {
33class SubtargetEmitter {
34  // Each processor has a SchedClassDesc table with an entry for each SchedClass.
35  // The SchedClassDesc table indexes into a global write resource table, write
36  // latency table, and read advance table.
37  struct SchedClassTables {
38    std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
39    std::vector<MCWriteProcResEntry> WriteProcResources;
40    std::vector<MCWriteLatencyEntry> WriteLatencies;
41    std::vector<std::string> WriterNames;
42    std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
43
44    // Reserve an invalid entry at index 0
45    SchedClassTables() {
46      ProcSchedClasses.resize(1);
47      WriteProcResources.resize(1);
48      WriteLatencies.resize(1);
49      WriterNames.push_back("InvalidWrite");
50      ReadAdvanceEntries.resize(1);
51    }
52  };
53
54  struct LessWriteProcResources {
55    bool operator()(const MCWriteProcResEntry &LHS,
56                    const MCWriteProcResEntry &RHS) {
57      return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
58    }
59  };
60
61  RecordKeeper &Records;
62  CodeGenSchedModels &SchedModels;
63  std::string Target;
64
65  void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
66  unsigned FeatureKeyValues(raw_ostream &OS);
67  unsigned CPUKeyValues(raw_ostream &OS);
68  void FormItineraryStageString(const std::string &Names,
69                                Record *ItinData, std::string &ItinString,
70                                unsigned &NStages);
71  void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
72                                       unsigned &NOperandCycles);
73  void FormItineraryBypassString(const std::string &Names,
74                                 Record *ItinData,
75                                 std::string &ItinString, unsigned NOperandCycles);
76  void EmitStageAndOperandCycleData(raw_ostream &OS,
77                                    std::vector<std::vector<InstrItinerary> >
78                                      &ProcItinLists);
79  void EmitItineraries(raw_ostream &OS,
80                       std::vector<std::vector<InstrItinerary> >
81                         &ProcItinLists);
82  void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
83                         char Separator);
84  void EmitProcessorResources(const CodeGenProcModel &ProcModel,
85                              raw_ostream &OS);
86  Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
87                             const CodeGenProcModel &ProcModel);
88  Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
89                          const CodeGenProcModel &ProcModel);
90  void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
91                           const CodeGenProcModel &ProcModel);
92  void GenSchedClassTables(const CodeGenProcModel &ProcModel,
93                           SchedClassTables &SchedTables);
94  void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
95  void EmitProcessorModels(raw_ostream &OS);
96  void EmitProcessorLookup(raw_ostream &OS);
97  void EmitSchedModelHelpers(std::string ClassName, raw_ostream &OS);
98  void EmitSchedModel(raw_ostream &OS);
99  void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
100                             unsigned NumProcs);
101
102public:
103  SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
104    Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
105
106  void run(raw_ostream &o);
107
108};
109} // End anonymous namespace
110
111//
112// Enumeration - Emit the specified class as an enumeration.
113//
114void SubtargetEmitter::Enumeration(raw_ostream &OS,
115                                   const char *ClassName,
116                                   bool isBits) {
117  // Get all records of class and sort
118  std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
119  std::sort(DefList.begin(), DefList.end(), LessRecord());
120
121  unsigned N = DefList.size();
122  if (N == 0)
123    return;
124  if (N > 64) {
125    errs() << "Too many (> 64) subtarget features!\n";
126    exit(1);
127  }
128
129  OS << "namespace " << Target << " {\n";
130
131  // For bit flag enumerations with more than 32 items, emit constants.
132  // Emit an enum for everything else.
133  if (isBits && N > 32) {
134    // For each record
135    for (unsigned i = 0; i < N; i++) {
136      // Next record
137      Record *Def = DefList[i];
138
139      // Get and emit name and expression (1 << i)
140      OS << "  const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
141    }
142  } else {
143    // Open enumeration
144    OS << "enum {\n";
145
146    // For each record
147    for (unsigned i = 0; i < N;) {
148      // Next record
149      Record *Def = DefList[i];
150
151      // Get and emit name
152      OS << "  " << Def->getName();
153
154      // If bit flags then emit expression (1 << i)
155      if (isBits)  OS << " = " << " 1ULL << " << i;
156
157      // Depending on 'if more in the list' emit comma
158      if (++i < N) OS << ",";
159
160      OS << "\n";
161    }
162
163    // Close enumeration
164    OS << "};\n";
165  }
166
167  OS << "}\n";
168}
169
170//
171// FeatureKeyValues - Emit data of all the subtarget features.  Used by the
172// command line.
173//
174unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
175  // Gather and sort all the features
176  std::vector<Record*> FeatureList =
177                           Records.getAllDerivedDefinitions("SubtargetFeature");
178
179  if (FeatureList.empty())
180    return 0;
181
182  std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
183
184  // Begin feature table
185  OS << "// Sorted (by key) array of values for CPU features.\n"
186     << "extern const llvm::SubtargetFeatureKV " << Target
187     << "FeatureKV[] = {\n";
188
189  // For each feature
190  unsigned NumFeatures = 0;
191  for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
192    // Next feature
193    Record *Feature = FeatureList[i];
194
195    const std::string &Name = Feature->getName();
196    const std::string &CommandLineName = Feature->getValueAsString("Name");
197    const std::string &Desc = Feature->getValueAsString("Desc");
198
199    if (CommandLineName.empty()) continue;
200
201    // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
202    OS << "  { "
203       << "\"" << CommandLineName << "\", "
204       << "\"" << Desc << "\", "
205       << Target << "::" << Name << ", ";
206
207    const std::vector<Record*> &ImpliesList =
208      Feature->getValueAsListOfDefs("Implies");
209
210    if (ImpliesList.empty()) {
211      OS << "0ULL";
212    } else {
213      for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
214        OS << Target << "::" << ImpliesList[j]->getName();
215        if (++j < M) OS << " | ";
216      }
217    }
218
219    OS << " }";
220    ++NumFeatures;
221
222    // Depending on 'if more in the list' emit comma
223    if ((i + 1) < N) OS << ",";
224
225    OS << "\n";
226  }
227
228  // End feature table
229  OS << "};\n";
230
231  return NumFeatures;
232}
233
234//
235// CPUKeyValues - Emit data of all the subtarget processors.  Used by command
236// line.
237//
238unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
239  // Gather and sort processor information
240  std::vector<Record*> ProcessorList =
241                          Records.getAllDerivedDefinitions("Processor");
242  std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
243
244  // Begin processor table
245  OS << "// Sorted (by key) array of values for CPU subtype.\n"
246     << "extern const llvm::SubtargetFeatureKV " << Target
247     << "SubTypeKV[] = {\n";
248
249  // For each processor
250  for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
251    // Next processor
252    Record *Processor = ProcessorList[i];
253
254    const std::string &Name = Processor->getValueAsString("Name");
255    const std::vector<Record*> &FeatureList =
256      Processor->getValueAsListOfDefs("Features");
257
258    // Emit as { "cpu", "description", f1 | f2 | ... fn },
259    OS << "  { "
260       << "\"" << Name << "\", "
261       << "\"Select the " << Name << " processor\", ";
262
263    if (FeatureList.empty()) {
264      OS << "0ULL";
265    } else {
266      for (unsigned j = 0, M = FeatureList.size(); j < M;) {
267        OS << Target << "::" << FeatureList[j]->getName();
268        if (++j < M) OS << " | ";
269      }
270    }
271
272    // The "0" is for the "implies" section of this data structure.
273    OS << ", 0ULL }";
274
275    // Depending on 'if more in the list' emit comma
276    if (++i < N) OS << ",";
277
278    OS << "\n";
279  }
280
281  // End processor table
282  OS << "};\n";
283
284  return ProcessorList.size();
285}
286
287//
288// FormItineraryStageString - Compose a string containing the stage
289// data initialization for the specified itinerary.  N is the number
290// of stages.
291//
292void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
293                                                Record *ItinData,
294                                                std::string &ItinString,
295                                                unsigned &NStages) {
296  // Get states list
297  const std::vector<Record*> &StageList =
298    ItinData->getValueAsListOfDefs("Stages");
299
300  // For each stage
301  unsigned N = NStages = StageList.size();
302  for (unsigned i = 0; i < N;) {
303    // Next stage
304    const Record *Stage = StageList[i];
305
306    // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
307    int Cycles = Stage->getValueAsInt("Cycles");
308    ItinString += "  { " + itostr(Cycles) + ", ";
309
310    // Get unit list
311    const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
312
313    // For each unit
314    for (unsigned j = 0, M = UnitList.size(); j < M;) {
315      // Add name and bitwise or
316      ItinString += Name + "FU::" + UnitList[j]->getName();
317      if (++j < M) ItinString += " | ";
318    }
319
320    int TimeInc = Stage->getValueAsInt("TimeInc");
321    ItinString += ", " + itostr(TimeInc);
322
323    int Kind = Stage->getValueAsInt("Kind");
324    ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
325
326    // Close off stage
327    ItinString += " }";
328    if (++i < N) ItinString += ", ";
329  }
330}
331
332//
333// FormItineraryOperandCycleString - Compose a string containing the
334// operand cycle initialization for the specified itinerary.  N is the
335// number of operands that has cycles specified.
336//
337void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
338                         std::string &ItinString, unsigned &NOperandCycles) {
339  // Get operand cycle list
340  const std::vector<int64_t> &OperandCycleList =
341    ItinData->getValueAsListOfInts("OperandCycles");
342
343  // For each operand cycle
344  unsigned N = NOperandCycles = OperandCycleList.size();
345  for (unsigned i = 0; i < N;) {
346    // Next operand cycle
347    const int OCycle = OperandCycleList[i];
348
349    ItinString += "  " + itostr(OCycle);
350    if (++i < N) ItinString += ", ";
351  }
352}
353
354void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
355                                                 Record *ItinData,
356                                                 std::string &ItinString,
357                                                 unsigned NOperandCycles) {
358  const std::vector<Record*> &BypassList =
359    ItinData->getValueAsListOfDefs("Bypasses");
360  unsigned N = BypassList.size();
361  unsigned i = 0;
362  for (; i < N;) {
363    ItinString += Name + "Bypass::" + BypassList[i]->getName();
364    if (++i < NOperandCycles) ItinString += ", ";
365  }
366  for (; i < NOperandCycles;) {
367    ItinString += " 0";
368    if (++i < NOperandCycles) ItinString += ", ";
369  }
370}
371
372//
373// EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
374// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
375// by CodeGenSchedClass::Index.
376//
377void SubtargetEmitter::
378EmitStageAndOperandCycleData(raw_ostream &OS,
379                             std::vector<std::vector<InstrItinerary> >
380                               &ProcItinLists) {
381
382  // Multiple processor models may share an itinerary record. Emit it once.
383  SmallPtrSet<Record*, 8> ItinsDefSet;
384
385  // Emit functional units for all the itineraries.
386  for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
387         PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
388
389    if (!ItinsDefSet.insert(PI->ItinsDef))
390      continue;
391
392    std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
393    if (FUs.empty())
394      continue;
395
396    const std::string &Name = PI->ItinsDef->getName();
397    OS << "\n// Functional units for \"" << Name << "\"\n"
398       << "namespace " << Name << "FU {\n";
399
400    for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
401      OS << "  const unsigned " << FUs[j]->getName()
402         << " = 1 << " << j << ";\n";
403
404    OS << "}\n";
405
406    std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");
407    if (BPs.size()) {
408      OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
409         << "\"\n" << "namespace " << Name << "Bypass {\n";
410
411      OS << "  const unsigned NoBypass = 0;\n";
412      for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
413        OS << "  const unsigned " << BPs[j]->getName()
414           << " = 1 << " << j << ";\n";
415
416      OS << "}\n";
417    }
418  }
419
420  // Begin stages table
421  std::string StageTable = "\nextern const llvm::InstrStage " + Target +
422                           "Stages[] = {\n";
423  StageTable += "  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
424
425  // Begin operand cycle table
426  std::string OperandCycleTable = "extern const unsigned " + Target +
427    "OperandCycles[] = {\n";
428  OperandCycleTable += "  0, // No itinerary\n";
429
430  // Begin pipeline bypass table
431  std::string BypassTable = "extern const unsigned " + Target +
432    "ForwardingPaths[] = {\n";
433  BypassTable += " 0, // No itinerary\n";
434
435  // For each Itinerary across all processors, add a unique entry to the stages,
436  // operand cycles, and pipepine bypess tables. Then add the new Itinerary
437  // object with computed offsets to the ProcItinLists result.
438  unsigned StageCount = 1, OperandCycleCount = 1;
439  std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
440  for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
441         PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
442    const CodeGenProcModel &ProcModel = *PI;
443
444    // Add process itinerary to the list.
445    ProcItinLists.resize(ProcItinLists.size()+1);
446
447    // If this processor defines no itineraries, then leave the itinerary list
448    // empty.
449    std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
450    if (!ProcModel.hasItineraries())
451      continue;
452
453    const std::string &Name = ProcModel.ItinsDef->getName();
454
455    ItinList.resize(SchedModels.numInstrSchedClasses());
456    assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
457
458    for (unsigned SchedClassIdx = 0, SchedClassEnd = ItinList.size();
459         SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
460
461      // Next itinerary data
462      Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
463
464      // Get string and stage count
465      std::string ItinStageString;
466      unsigned NStages = 0;
467      if (ItinData)
468        FormItineraryStageString(Name, ItinData, ItinStageString, NStages);
469
470      // Get string and operand cycle count
471      std::string ItinOperandCycleString;
472      unsigned NOperandCycles = 0;
473      std::string ItinBypassString;
474      if (ItinData) {
475        FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
476                                        NOperandCycles);
477
478        FormItineraryBypassString(Name, ItinData, ItinBypassString,
479                                  NOperandCycles);
480      }
481
482      // Check to see if stage already exists and create if it doesn't
483      unsigned FindStage = 0;
484      if (NStages > 0) {
485        FindStage = ItinStageMap[ItinStageString];
486        if (FindStage == 0) {
487          // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
488          StageTable += ItinStageString + ", // " + itostr(StageCount);
489          if (NStages > 1)
490            StageTable += "-" + itostr(StageCount + NStages - 1);
491          StageTable += "\n";
492          // Record Itin class number.
493          ItinStageMap[ItinStageString] = FindStage = StageCount;
494          StageCount += NStages;
495        }
496      }
497
498      // Check to see if operand cycle already exists and create if it doesn't
499      unsigned FindOperandCycle = 0;
500      if (NOperandCycles > 0) {
501        std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
502        FindOperandCycle = ItinOperandMap[ItinOperandString];
503        if (FindOperandCycle == 0) {
504          // Emit as  cycle, // index
505          OperandCycleTable += ItinOperandCycleString + ", // ";
506          std::string OperandIdxComment = itostr(OperandCycleCount);
507          if (NOperandCycles > 1)
508            OperandIdxComment += "-"
509              + itostr(OperandCycleCount + NOperandCycles - 1);
510          OperandCycleTable += OperandIdxComment + "\n";
511          // Record Itin class number.
512          ItinOperandMap[ItinOperandCycleString] =
513            FindOperandCycle = OperandCycleCount;
514          // Emit as bypass, // index
515          BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
516          OperandCycleCount += NOperandCycles;
517        }
518      }
519
520      // Set up itinerary as location and location + stage count
521      int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
522      InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
523                                    FindOperandCycle,
524                                    FindOperandCycle + NOperandCycles};
525
526      // Inject - empty slots will be 0, 0
527      ItinList[SchedClassIdx] = Intinerary;
528    }
529  }
530
531  // Closing stage
532  StageTable += "  { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
533  StageTable += "};\n";
534
535  // Closing operand cycles
536  OperandCycleTable += "  0 // End operand cycles\n";
537  OperandCycleTable += "};\n";
538
539  BypassTable += " 0 // End bypass tables\n";
540  BypassTable += "};\n";
541
542  // Emit tables.
543  OS << StageTable;
544  OS << OperandCycleTable;
545  OS << BypassTable;
546}
547
548//
549// EmitProcessorData - Generate data for processor itineraries that were
550// computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
551// Itineraries for each processor. The Itinerary lists are indexed on
552// CodeGenSchedClass::Index.
553//
554void SubtargetEmitter::
555EmitItineraries(raw_ostream &OS,
556                std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
557
558  // Multiple processor models may share an itinerary record. Emit it once.
559  SmallPtrSet<Record*, 8> ItinsDefSet;
560
561  // For each processor's machine model
562  std::vector<std::vector<InstrItinerary> >::iterator
563      ProcItinListsIter = ProcItinLists.begin();
564  for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
565         PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
566
567    Record *ItinsDef = PI->ItinsDef;
568    if (!ItinsDefSet.insert(ItinsDef))
569      continue;
570
571    // Get processor itinerary name
572    const std::string &Name = ItinsDef->getName();
573
574    // Get the itinerary list for the processor.
575    assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
576    std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
577
578    OS << "\n";
579    OS << "static const llvm::InstrItinerary ";
580    if (ItinList.empty()) {
581      OS << '*' << Name << " = 0;\n";
582      continue;
583    }
584
585    // Begin processor itinerary table
586    OS << Name << "[] = {\n";
587
588    // For each itinerary class in CodeGenSchedClass::Index order.
589    for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
590      InstrItinerary &Intinerary = ItinList[j];
591
592      // Emit Itinerary in the form of
593      // { firstStage, lastStage, firstCycle, lastCycle } // index
594      OS << "  { " <<
595        Intinerary.NumMicroOps << ", " <<
596        Intinerary.FirstStage << ", " <<
597        Intinerary.LastStage << ", " <<
598        Intinerary.FirstOperandCycle << ", " <<
599        Intinerary.LastOperandCycle << " }" <<
600        ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
601    }
602    // End processor itinerary table
603    OS << "  { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
604    OS << "};\n";
605  }
606}
607
608// Emit either the value defined in the TableGen Record, or the default
609// value defined in the C++ header. The Record is null if the processor does not
610// define a model.
611void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
612                                         const char *Name, char Separator) {
613  OS << "  ";
614  int V = R ? R->getValueAsInt(Name) : -1;
615  if (V >= 0)
616    OS << V << Separator << " // " << Name;
617  else
618    OS << "MCSchedModel::Default" << Name << Separator;
619  OS << '\n';
620}
621
622void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
623                                              raw_ostream &OS) {
624  char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
625
626  OS << "\n// {Name, NumUnits, SuperIdx, IsBuffered}\n";
627  OS << "static const llvm::MCProcResourceDesc "
628     << ProcModel.ModelName << "ProcResources" << "[] = {\n"
629     << "  {DBGFIELD(\"InvalidUnit\")     0, 0, 0}" << Sep << "\n";
630
631  for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
632    Record *PRDef = ProcModel.ProcResourceDefs[i];
633
634    Record *SuperDef = 0;
635    unsigned SuperIdx = 0;
636    unsigned NumUnits = 0;
637    bool IsBuffered = true;
638    if (PRDef->isSubClassOf("ProcResGroup")) {
639      RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
640      for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end();
641           RUI != RUE; ++RUI) {
642        if (!NumUnits)
643          IsBuffered = (*RUI)->getValueAsBit("Buffered");
644        else if(IsBuffered != (*RUI)->getValueAsBit("Buffered"))
645          PrintFatalError(PRDef->getLoc(),
646                          "Mixing buffered and unbuffered resources.");
647        NumUnits += (*RUI)->getValueAsInt("NumUnits");
648      }
649    }
650    else {
651      // Find the SuperIdx
652      if (PRDef->getValueInit("Super")->isComplete()) {
653        SuperDef = SchedModels.findProcResUnits(
654          PRDef->getValueAsDef("Super"), ProcModel);
655        SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
656      }
657      NumUnits = PRDef->getValueAsInt("NumUnits");
658      IsBuffered = PRDef->getValueAsBit("Buffered");
659    }
660    // Emit the ProcResourceDesc
661    if (i+1 == e)
662      Sep = ' ';
663    OS << "  {DBGFIELD(\"" << PRDef->getName() << "\") ";
664    if (PRDef->getName().size() < 15)
665      OS.indent(15 - PRDef->getName().size());
666    OS << NumUnits << ", " << SuperIdx << ", "
667       << IsBuffered << "}" << Sep << " // #" << i+1;
668    if (SuperDef)
669      OS << ", Super=" << SuperDef->getName();
670    OS << "\n";
671  }
672  OS << "};\n";
673}
674
675// Find the WriteRes Record that defines processor resources for this
676// SchedWrite.
677Record *SubtargetEmitter::FindWriteResources(
678  const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
679
680  // Check if the SchedWrite is already subtarget-specific and directly
681  // specifies a set of processor resources.
682  if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
683    return SchedWrite.TheDef;
684
685  Record *AliasDef = 0;
686  for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
687       AI != AE; ++AI) {
688    const CodeGenSchedRW &AliasRW =
689      SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
690    if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
691      Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
692      if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
693        continue;
694    }
695    if (AliasDef)
696      PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
697                    "defined for processor " + ProcModel.ModelName +
698                    " Ensure only one SchedAlias exists per RW.");
699    AliasDef = AliasRW.TheDef;
700  }
701  if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes"))
702    return AliasDef;
703
704  // Check this processor's list of write resources.
705  Record *ResDef = 0;
706  for (RecIter WRI = ProcModel.WriteResDefs.begin(),
707         WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
708    if (!(*WRI)->isSubClassOf("WriteRes"))
709      continue;
710    if (AliasDef == (*WRI)->getValueAsDef("WriteType")
711        || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) {
712      if (ResDef) {
713        PrintFatalError((*WRI)->getLoc(), "Resources are defined for both "
714                      "SchedWrite and its alias on processor " +
715                      ProcModel.ModelName);
716      }
717      ResDef = *WRI;
718    }
719  }
720  // TODO: If ProcModel has a base model (previous generation processor),
721  // then call FindWriteResources recursively with that model here.
722  if (!ResDef) {
723    PrintFatalError(ProcModel.ModelDef->getLoc(),
724                  std::string("Processor does not define resources for ")
725                  + SchedWrite.TheDef->getName());
726  }
727  return ResDef;
728}
729
730/// Find the ReadAdvance record for the given SchedRead on this processor or
731/// return NULL.
732Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
733                                          const CodeGenProcModel &ProcModel) {
734  // Check for SchedReads that directly specify a ReadAdvance.
735  if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
736    return SchedRead.TheDef;
737
738  // Check this processor's list of aliases for SchedRead.
739  Record *AliasDef = 0;
740  for (RecIter AI = SchedRead.Aliases.begin(), AE = SchedRead.Aliases.end();
741       AI != AE; ++AI) {
742    const CodeGenSchedRW &AliasRW =
743      SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
744    if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
745      Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
746      if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
747        continue;
748    }
749    if (AliasDef)
750      PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
751                    "defined for processor " + ProcModel.ModelName +
752                    " Ensure only one SchedAlias exists per RW.");
753    AliasDef = AliasRW.TheDef;
754  }
755  if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance"))
756    return AliasDef;
757
758  // Check this processor's ReadAdvanceList.
759  Record *ResDef = 0;
760  for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
761         RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
762    if (!(*RAI)->isSubClassOf("ReadAdvance"))
763      continue;
764    if (AliasDef == (*RAI)->getValueAsDef("ReadType")
765        || SchedRead.TheDef == (*RAI)->getValueAsDef("ReadType")) {
766      if (ResDef) {
767        PrintFatalError((*RAI)->getLoc(), "Resources are defined for both "
768                      "SchedRead and its alias on processor " +
769                      ProcModel.ModelName);
770      }
771      ResDef = *RAI;
772    }
773  }
774  // TODO: If ProcModel has a base model (previous generation processor),
775  // then call FindReadAdvance recursively with that model here.
776  if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") {
777    PrintFatalError(ProcModel.ModelDef->getLoc(),
778                  std::string("Processor does not define resources for ")
779                  + SchedRead.TheDef->getName());
780  }
781  return ResDef;
782}
783
784// Expand an explicit list of processor resources into a full list of implied
785// resource groups and super resources that cover them.
786void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
787                                           std::vector<int64_t> &Cycles,
788                                           const CodeGenProcModel &PM) {
789  // Default to 1 resource cycle.
790  Cycles.resize(PRVec.size(), 1);
791  for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
792    Record *PRDef = PRVec[i];
793    RecVec SubResources;
794    if (PRDef->isSubClassOf("ProcResGroup"))
795      SubResources = PRDef->getValueAsListOfDefs("Resources");
796    else {
797      SubResources.push_back(PRDef);
798      PRDef = SchedModels.findProcResUnits(PRVec[i], PM);
799      for (Record *SubDef = PRDef;
800           SubDef->getValueInit("Super")->isComplete();) {
801        if (SubDef->isSubClassOf("ProcResGroup")) {
802          // Disallow this for simplicitly.
803          PrintFatalError(SubDef->getLoc(), "Processor resource group "
804                          " cannot be a super resources.");
805        }
806        Record *SuperDef =
807          SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM);
808        PRVec.push_back(SuperDef);
809        Cycles.push_back(Cycles[i]);
810        SubDef = SuperDef;
811      }
812    }
813    for (RecIter PRI = PM.ProcResourceDefs.begin(),
814           PRE = PM.ProcResourceDefs.end();
815         PRI != PRE; ++PRI) {
816      if (*PRI == PRDef || !(*PRI)->isSubClassOf("ProcResGroup"))
817        continue;
818      RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
819      RecIter SubI = SubResources.begin(), SubE = SubResources.end();
820      for( ; SubI != SubE; ++SubI) {
821        if (std::find(SuperResources.begin(), SuperResources.end(), *SubI)
822            == SuperResources.end()) {
823          break;
824        }
825      }
826      if (SubI == SubE) {
827        PRVec.push_back(*PRI);
828        Cycles.push_back(Cycles[i]);
829      }
830    }
831  }
832}
833
834// Generate the SchedClass table for this processor and update global
835// tables. Must be called for each processor in order.
836void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
837                                           SchedClassTables &SchedTables) {
838  SchedTables.ProcSchedClasses.resize(SchedTables.ProcSchedClasses.size() + 1);
839  if (!ProcModel.hasInstrSchedModel())
840    return;
841
842  std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
843  for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
844         SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
845    DEBUG(SCI->dump(&SchedModels));
846
847    SCTab.resize(SCTab.size() + 1);
848    MCSchedClassDesc &SCDesc = SCTab.back();
849    // SCDesc.Name is guarded by NDEBUG
850    SCDesc.NumMicroOps = 0;
851    SCDesc.BeginGroup = false;
852    SCDesc.EndGroup = false;
853    SCDesc.WriteProcResIdx = 0;
854    SCDesc.WriteLatencyIdx = 0;
855    SCDesc.ReadAdvanceIdx = 0;
856
857    // A Variant SchedClass has no resources of its own.
858    bool HasVariants = false;
859    for (std::vector<CodeGenSchedTransition>::const_iterator
860           TI = SCI->Transitions.begin(), TE = SCI->Transitions.end();
861         TI != TE; ++TI) {
862      if (TI->ProcIndices[0] == 0) {
863        HasVariants = true;
864        break;
865      }
866      IdxIter PIPos = std::find(TI->ProcIndices.begin(),
867                                TI->ProcIndices.end(), ProcModel.Index);
868      if (PIPos != TI->ProcIndices.end()) {
869        HasVariants = true;
870        break;
871      }
872    }
873    if (HasVariants) {
874      SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
875      continue;
876    }
877
878    // Determine if the SchedClass is actually reachable on this processor. If
879    // not don't try to locate the processor resources, it will fail.
880    // If ProcIndices contains 0, this class applies to all processors.
881    assert(!SCI->ProcIndices.empty() && "expect at least one procidx");
882    if (SCI->ProcIndices[0] != 0) {
883      IdxIter PIPos = std::find(SCI->ProcIndices.begin(),
884                                SCI->ProcIndices.end(), ProcModel.Index);
885      if (PIPos == SCI->ProcIndices.end())
886        continue;
887    }
888    IdxVec Writes = SCI->Writes;
889    IdxVec Reads = SCI->Reads;
890    if (!SCI->InstRWs.empty()) {
891      // This class has a default ReadWrite list which can be overriden by
892      // InstRW definitions.
893      Record *RWDef = 0;
894      for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
895           RWI != RWE; ++RWI) {
896        Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
897        if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
898          RWDef = *RWI;
899          break;
900        }
901      }
902      if (RWDef) {
903        Writes.clear();
904        Reads.clear();
905        SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
906                            Writes, Reads);
907      }
908    }
909    if (Writes.empty()) {
910      // Check this processor's itinerary class resources.
911      for (RecIter II = ProcModel.ItinRWDefs.begin(),
912             IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {
913        RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
914        if (std::find(Matched.begin(), Matched.end(), SCI->ItinClassDef)
915            != Matched.end()) {
916          SchedModels.findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"),
917                              Writes, Reads);
918          break;
919        }
920      }
921      if (Writes.empty()) {
922        DEBUG(dbgs() << ProcModel.ModelName
923              << " does not have resources for class " << SCI->Name << '\n');
924      }
925    }
926    // Sum resources across all operand writes.
927    std::vector<MCWriteProcResEntry> WriteProcResources;
928    std::vector<MCWriteLatencyEntry> WriteLatencies;
929    std::vector<std::string> WriterNames;
930    std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
931    for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
932      IdxVec WriteSeq;
933      SchedModels.expandRWSeqForProc(*WI, WriteSeq, /*IsRead=*/false,
934                                     ProcModel);
935
936      // For each operand, create a latency entry.
937      MCWriteLatencyEntry WLEntry;
938      WLEntry.Cycles = 0;
939      unsigned WriteID = WriteSeq.back();
940      WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
941      // If this Write is not referenced by a ReadAdvance, don't distinguish it
942      // from other WriteLatency entries.
943      if (!SchedModels.hasReadOfWrite(
944            SchedModels.getSchedWrite(WriteID).TheDef)) {
945        WriteID = 0;
946      }
947      WLEntry.WriteResourceID = WriteID;
948
949      for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end();
950           WSI != WSE; ++WSI) {
951
952        Record *WriteRes =
953          FindWriteResources(SchedModels.getSchedWrite(*WSI), ProcModel);
954
955        // Mark the parent class as invalid for unsupported write types.
956        if (WriteRes->getValueAsBit("Unsupported")) {
957          SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
958          break;
959        }
960        WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
961        SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps");
962        SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");
963        SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
964
965        // Create an entry for each ProcResource listed in WriteRes.
966        RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
967        std::vector<int64_t> Cycles =
968          WriteRes->getValueAsListOfInts("ResourceCycles");
969
970        ExpandProcResources(PRVec, Cycles, ProcModel);
971
972        for (unsigned PRIdx = 0, PREnd = PRVec.size();
973             PRIdx != PREnd; ++PRIdx) {
974          MCWriteProcResEntry WPREntry;
975          WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
976          assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
977          WPREntry.Cycles = Cycles[PRIdx];
978          // If this resource is already used in this sequence, add the current
979          // entry's cycles so that the same resource appears to be used
980          // serially, rather than multiple parallel uses. This is important for
981          // in-order machine where the resource consumption is a hazard.
982          unsigned WPRIdx = 0, WPREnd = WriteProcResources.size();
983          for( ; WPRIdx != WPREnd; ++WPRIdx) {
984            if (WriteProcResources[WPRIdx].ProcResourceIdx
985                == WPREntry.ProcResourceIdx) {
986              WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
987              break;
988            }
989          }
990          if (WPRIdx == WPREnd)
991            WriteProcResources.push_back(WPREntry);
992        }
993      }
994      WriteLatencies.push_back(WLEntry);
995    }
996    // Create an entry for each operand Read in this SchedClass.
997    // Entries must be sorted first by UseIdx then by WriteResourceID.
998    for (unsigned UseIdx = 0, EndIdx = Reads.size();
999         UseIdx != EndIdx; ++UseIdx) {
1000      Record *ReadAdvance =
1001        FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
1002      if (!ReadAdvance)
1003        continue;
1004
1005      // Mark the parent class as invalid for unsupported write types.
1006      if (ReadAdvance->getValueAsBit("Unsupported")) {
1007        SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
1008        break;
1009      }
1010      RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");
1011      IdxVec WriteIDs;
1012      if (ValidWrites.empty())
1013        WriteIDs.push_back(0);
1014      else {
1015        for (RecIter VWI = ValidWrites.begin(), VWE = ValidWrites.end();
1016             VWI != VWE; ++VWI) {
1017          WriteIDs.push_back(SchedModels.getSchedRWIdx(*VWI, /*IsRead=*/false));
1018        }
1019      }
1020      std::sort(WriteIDs.begin(), WriteIDs.end());
1021      for(IdxIter WI = WriteIDs.begin(), WE = WriteIDs.end(); WI != WE; ++WI) {
1022        MCReadAdvanceEntry RAEntry;
1023        RAEntry.UseIdx = UseIdx;
1024        RAEntry.WriteResourceID = *WI;
1025        RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
1026        ReadAdvanceEntries.push_back(RAEntry);
1027      }
1028    }
1029    if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
1030      WriteProcResources.clear();
1031      WriteLatencies.clear();
1032      ReadAdvanceEntries.clear();
1033    }
1034    // Add the information for this SchedClass to the global tables using basic
1035    // compression.
1036    //
1037    // WritePrecRes entries are sorted by ProcResIdx.
1038    std::sort(WriteProcResources.begin(), WriteProcResources.end(),
1039              LessWriteProcResources());
1040
1041    SCDesc.NumWriteProcResEntries = WriteProcResources.size();
1042    std::vector<MCWriteProcResEntry>::iterator WPRPos =
1043      std::search(SchedTables.WriteProcResources.begin(),
1044                  SchedTables.WriteProcResources.end(),
1045                  WriteProcResources.begin(), WriteProcResources.end());
1046    if (WPRPos != SchedTables.WriteProcResources.end())
1047      SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
1048    else {
1049      SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
1050      SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(),
1051                                            WriteProcResources.end());
1052    }
1053    // Latency entries must remain in operand order.
1054    SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
1055    std::vector<MCWriteLatencyEntry>::iterator WLPos =
1056      std::search(SchedTables.WriteLatencies.begin(),
1057                  SchedTables.WriteLatencies.end(),
1058                  WriteLatencies.begin(), WriteLatencies.end());
1059    if (WLPos != SchedTables.WriteLatencies.end()) {
1060      unsigned idx = WLPos - SchedTables.WriteLatencies.begin();
1061      SCDesc.WriteLatencyIdx = idx;
1062      for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i)
1063        if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) ==
1064            std::string::npos) {
1065          SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i];
1066        }
1067    }
1068    else {
1069      SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
1070      SchedTables.WriteLatencies.insert(SchedTables.WriteLatencies.end(),
1071                                        WriteLatencies.begin(),
1072                                        WriteLatencies.end());
1073      SchedTables.WriterNames.insert(SchedTables.WriterNames.end(),
1074                                     WriterNames.begin(), WriterNames.end());
1075    }
1076    // ReadAdvanceEntries must remain in operand order.
1077    SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
1078    std::vector<MCReadAdvanceEntry>::iterator RAPos =
1079      std::search(SchedTables.ReadAdvanceEntries.begin(),
1080                  SchedTables.ReadAdvanceEntries.end(),
1081                  ReadAdvanceEntries.begin(), ReadAdvanceEntries.end());
1082    if (RAPos != SchedTables.ReadAdvanceEntries.end())
1083      SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
1084    else {
1085      SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
1086      SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(),
1087                                            ReadAdvanceEntries.end());
1088    }
1089  }
1090}
1091
1092// Emit SchedClass tables for all processors and associated global tables.
1093void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
1094                                            raw_ostream &OS) {
1095  // Emit global WriteProcResTable.
1096  OS << "\n// {ProcResourceIdx, Cycles}\n"
1097     << "extern const llvm::MCWriteProcResEntry "
1098     << Target << "WriteProcResTable[] = {\n"
1099     << "  { 0,  0}, // Invalid\n";
1100  for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
1101       WPRIdx != WPREnd; ++WPRIdx) {
1102    MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
1103    OS << "  {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
1104       << format("%2d", WPREntry.Cycles) << "}";
1105    if (WPRIdx + 1 < WPREnd)
1106      OS << ',';
1107    OS << " // #" << WPRIdx << '\n';
1108  }
1109  OS << "}; // " << Target << "WriteProcResTable\n";
1110
1111  // Emit global WriteLatencyTable.
1112  OS << "\n// {Cycles, WriteResourceID}\n"
1113     << "extern const llvm::MCWriteLatencyEntry "
1114     << Target << "WriteLatencyTable[] = {\n"
1115     << "  { 0,  0}, // Invalid\n";
1116  for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
1117       WLIdx != WLEnd; ++WLIdx) {
1118    MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
1119    OS << "  {" << format("%2d", WLEntry.Cycles) << ", "
1120       << format("%2d", WLEntry.WriteResourceID) << "}";
1121    if (WLIdx + 1 < WLEnd)
1122      OS << ',';
1123    OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
1124  }
1125  OS << "}; // " << Target << "WriteLatencyTable\n";
1126
1127  // Emit global ReadAdvanceTable.
1128  OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
1129     << "extern const llvm::MCReadAdvanceEntry "
1130     << Target << "ReadAdvanceTable[] = {\n"
1131     << "  {0,  0,  0}, // Invalid\n";
1132  for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
1133       RAIdx != RAEnd; ++RAIdx) {
1134    MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
1135    OS << "  {" << RAEntry.UseIdx << ", "
1136       << format("%2d", RAEntry.WriteResourceID) << ", "
1137       << format("%2d", RAEntry.Cycles) << "}";
1138    if (RAIdx + 1 < RAEnd)
1139      OS << ',';
1140    OS << " // #" << RAIdx << '\n';
1141  }
1142  OS << "}; // " << Target << "ReadAdvanceTable\n";
1143
1144  // Emit a SchedClass table for each processor.
1145  for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1146         PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1147    if (!PI->hasInstrSchedModel())
1148      continue;
1149
1150    std::vector<MCSchedClassDesc> &SCTab =
1151      SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())];
1152
1153    OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
1154       << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
1155    OS << "static const llvm::MCSchedClassDesc "
1156       << PI->ModelName << "SchedClasses[] = {\n";
1157
1158    // The first class is always invalid. We no way to distinguish it except by
1159    // name and position.
1160    assert(SchedModels.getSchedClass(0).Name == "NoInstrModel"
1161           && "invalid class not first");
1162    OS << "  {DBGFIELD(\"InvalidSchedClass\")  "
1163       << MCSchedClassDesc::InvalidNumMicroOps
1164       << ", 0, 0,  0, 0,  0, 0,  0, 0},\n";
1165
1166    for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
1167      MCSchedClassDesc &MCDesc = SCTab[SCIdx];
1168      const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
1169      OS << "  {DBGFIELD(\"" << SchedClass.Name << "\") ";
1170      if (SchedClass.Name.size() < 18)
1171        OS.indent(18 - SchedClass.Name.size());
1172      OS << MCDesc.NumMicroOps
1173         << ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup
1174         << ", " << format("%2d", MCDesc.WriteProcResIdx)
1175         << ", " << MCDesc.NumWriteProcResEntries
1176         << ", " << format("%2d", MCDesc.WriteLatencyIdx)
1177         << ", " << MCDesc.NumWriteLatencyEntries
1178         << ", " << format("%2d", MCDesc.ReadAdvanceIdx)
1179         << ", " << MCDesc.NumReadAdvanceEntries << "}";
1180      if (SCIdx + 1 < SCEnd)
1181        OS << ',';
1182      OS << " // #" << SCIdx << '\n';
1183    }
1184    OS << "}; // " << PI->ModelName << "SchedClasses\n";
1185  }
1186}
1187
1188void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
1189  // For each processor model.
1190  for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1191         PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1192    // Emit processor resource table.
1193    if (PI->hasInstrSchedModel())
1194      EmitProcessorResources(*PI, OS);
1195    else if(!PI->ProcResourceDefs.empty())
1196      PrintFatalError(PI->ModelDef->getLoc(), "SchedMachineModel defines "
1197                    "ProcResources without defining WriteRes SchedWriteRes");
1198
1199    // Begin processor itinerary properties
1200    OS << "\n";
1201    OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
1202    EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
1203    EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
1204    EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
1205    EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
1206    EmitProcessorProp(OS, PI->ModelDef, "ILPWindow", ',');
1207    EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
1208    OS << "  " << PI->Index << ", // Processor ID\n";
1209    if (PI->hasInstrSchedModel())
1210      OS << "  " << PI->ModelName << "ProcResources" << ",\n"
1211         << "  " << PI->ModelName << "SchedClasses" << ",\n"
1212         << "  " << PI->ProcResourceDefs.size()+1 << ",\n"
1213         << "  " << (SchedModels.schedClassEnd()
1214                     - SchedModels.schedClassBegin()) << ",\n";
1215    else
1216      OS << "  0, 0, 0, 0, // No instruction-level machine model.\n";
1217    if (SchedModels.hasItineraries())
1218      OS << "  " << PI->ItinsDef->getName() << ");\n";
1219    else
1220      OS << "  0); // No Itinerary\n";
1221  }
1222}
1223
1224//
1225// EmitProcessorLookup - generate cpu name to itinerary lookup table.
1226//
1227void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
1228  // Gather and sort processor information
1229  std::vector<Record*> ProcessorList =
1230                          Records.getAllDerivedDefinitions("Processor");
1231  std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
1232
1233  // Begin processor table
1234  OS << "\n";
1235  OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
1236     << "extern const llvm::SubtargetInfoKV "
1237     << Target << "ProcSchedKV[] = {\n";
1238
1239  // For each processor
1240  for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
1241    // Next processor
1242    Record *Processor = ProcessorList[i];
1243
1244    const std::string &Name = Processor->getValueAsString("Name");
1245    const std::string &ProcModelName =
1246      SchedModels.getModelForProc(Processor).ModelName;
1247
1248    // Emit as { "cpu", procinit },
1249    OS << "  { \"" << Name << "\", (const void *)&" << ProcModelName << " }";
1250
1251    // Depending on ''if more in the list'' emit comma
1252    if (++i < N) OS << ",";
1253
1254    OS << "\n";
1255  }
1256
1257  // End processor table
1258  OS << "};\n";
1259}
1260
1261//
1262// EmitSchedModel - Emits all scheduling model tables, folding common patterns.
1263//
1264void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
1265  OS << "#ifdef DBGFIELD\n"
1266     << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
1267     << "#endif\n"
1268     << "#ifndef NDEBUG\n"
1269     << "#define DBGFIELD(x) x,\n"
1270     << "#else\n"
1271     << "#define DBGFIELD(x)\n"
1272     << "#endif\n";
1273
1274  if (SchedModels.hasItineraries()) {
1275    std::vector<std::vector<InstrItinerary> > ProcItinLists;
1276    // Emit the stage data
1277    EmitStageAndOperandCycleData(OS, ProcItinLists);
1278    EmitItineraries(OS, ProcItinLists);
1279  }
1280  OS << "\n// ===============================================================\n"
1281     << "// Data tables for the new per-operand machine model.\n";
1282
1283  SchedClassTables SchedTables;
1284  for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1285         PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1286    GenSchedClassTables(*PI, SchedTables);
1287  }
1288  EmitSchedClassTables(SchedTables, OS);
1289
1290  // Emit the processor machine model
1291  EmitProcessorModels(OS);
1292  // Emit the processor lookup data
1293  EmitProcessorLookup(OS);
1294
1295  OS << "#undef DBGFIELD";
1296}
1297
1298void SubtargetEmitter::EmitSchedModelHelpers(std::string ClassName,
1299                                             raw_ostream &OS) {
1300  OS << "unsigned " << ClassName
1301     << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
1302     << " const TargetSchedModel *SchedModel) const {\n";
1303
1304  std::vector<Record*> Prologs = Records.getAllDerivedDefinitions("PredicateProlog");
1305  std::sort(Prologs.begin(), Prologs.end(), LessRecord());
1306  for (std::vector<Record*>::const_iterator
1307         PI = Prologs.begin(), PE = Prologs.end(); PI != PE; ++PI) {
1308    OS << (*PI)->getValueAsString("Code") << '\n';
1309  }
1310  IdxVec VariantClasses;
1311  for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
1312         SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
1313    if (SCI->Transitions.empty())
1314      continue;
1315    VariantClasses.push_back(SCI->Index);
1316  }
1317  if (!VariantClasses.empty()) {
1318    OS << "  switch (SchedClass) {\n";
1319    for (IdxIter VCI = VariantClasses.begin(), VCE = VariantClasses.end();
1320         VCI != VCE; ++VCI) {
1321      const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI);
1322      OS << "  case " << *VCI << ": // " << SC.Name << '\n';
1323      IdxVec ProcIndices;
1324      for (std::vector<CodeGenSchedTransition>::const_iterator
1325             TI = SC.Transitions.begin(), TE = SC.Transitions.end();
1326           TI != TE; ++TI) {
1327        IdxVec PI;
1328        std::set_union(TI->ProcIndices.begin(), TI->ProcIndices.end(),
1329                       ProcIndices.begin(), ProcIndices.end(),
1330                       std::back_inserter(PI));
1331        ProcIndices.swap(PI);
1332      }
1333      for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
1334           PI != PE; ++PI) {
1335        OS << "    ";
1336        if (*PI != 0)
1337          OS << "if (SchedModel->getProcessorID() == " << *PI << ") ";
1338        OS << "{ // " << (SchedModels.procModelBegin() + *PI)->ModelName
1339           << '\n';
1340        for (std::vector<CodeGenSchedTransition>::const_iterator
1341               TI = SC.Transitions.begin(), TE = SC.Transitions.end();
1342             TI != TE; ++TI) {
1343          OS << "      if (";
1344          if (*PI != 0 && !std::count(TI->ProcIndices.begin(),
1345                                      TI->ProcIndices.end(), *PI)) {
1346              continue;
1347          }
1348          for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end();
1349               RI != RE; ++RI) {
1350            if (RI != TI->PredTerm.begin())
1351              OS << "\n          && ";
1352            OS << "(" << (*RI)->getValueAsString("Predicate") << ")";
1353          }
1354          OS << ")\n"
1355             << "        return " << TI->ToClassIdx << "; // "
1356             << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n';
1357        }
1358        OS << "    }\n";
1359        if (*PI == 0)
1360          break;
1361      }
1362      if (SC.isInferred())
1363        OS << "    return " << SC.Index << ";\n";
1364      OS << "    break;\n";
1365    }
1366    OS << "  };\n";
1367  }
1368  OS << "  report_fatal_error(\"Expected a variant SchedClass\");\n"
1369     << "} // " << ClassName << "::resolveSchedClass\n";
1370}
1371
1372//
1373// ParseFeaturesFunction - Produces a subtarget specific function for parsing
1374// the subtarget features string.
1375//
1376void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
1377                                             unsigned NumFeatures,
1378                                             unsigned NumProcs) {
1379  std::vector<Record*> Features =
1380                       Records.getAllDerivedDefinitions("SubtargetFeature");
1381  std::sort(Features.begin(), Features.end(), LessRecord());
1382
1383  OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1384     << "// subtarget options.\n"
1385     << "void llvm::";
1386  OS << Target;
1387  OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
1388     << "  DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
1389     << "  DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
1390
1391  if (Features.empty()) {
1392    OS << "}\n";
1393    return;
1394  }
1395
1396  OS << "  InitMCProcessorInfo(CPU, FS);\n"
1397     << "  uint64_t Bits = getFeatureBits();\n";
1398
1399  for (unsigned i = 0; i < Features.size(); i++) {
1400    // Next record
1401    Record *R = Features[i];
1402    const std::string &Instance = R->getName();
1403    const std::string &Value = R->getValueAsString("Value");
1404    const std::string &Attribute = R->getValueAsString("Attribute");
1405
1406    if (Value=="true" || Value=="false")
1407      OS << "  if ((Bits & " << Target << "::"
1408         << Instance << ") != 0) "
1409         << Attribute << " = " << Value << ";\n";
1410    else
1411      OS << "  if ((Bits & " << Target << "::"
1412         << Instance << ") != 0 && "
1413         << Attribute << " < " << Value << ") "
1414         << Attribute << " = " << Value << ";\n";
1415  }
1416
1417  OS << "}\n";
1418}
1419
1420//
1421// SubtargetEmitter::run - Main subtarget enumeration emitter.
1422//
1423void SubtargetEmitter::run(raw_ostream &OS) {
1424  emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
1425
1426  OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
1427  OS << "#undef GET_SUBTARGETINFO_ENUM\n";
1428
1429  OS << "namespace llvm {\n";
1430  Enumeration(OS, "SubtargetFeature", true);
1431  OS << "} // End llvm namespace \n";
1432  OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
1433
1434  OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
1435  OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
1436
1437  OS << "namespace llvm {\n";
1438#if 0
1439  OS << "namespace {\n";
1440#endif
1441  unsigned NumFeatures = FeatureKeyValues(OS);
1442  OS << "\n";
1443  unsigned NumProcs = CPUKeyValues(OS);
1444  OS << "\n";
1445  EmitSchedModel(OS);
1446  OS << "\n";
1447#if 0
1448  OS << "}\n";
1449#endif
1450
1451  // MCInstrInfo initialization routine.
1452  OS << "static inline void Init" << Target
1453     << "MCSubtargetInfo(MCSubtargetInfo *II, "
1454     << "StringRef TT, StringRef CPU, StringRef FS) {\n";
1455  OS << "  II->InitMCSubtargetInfo(TT, CPU, FS, ";
1456  if (NumFeatures)
1457    OS << Target << "FeatureKV, ";
1458  else
1459    OS << "0, ";
1460  if (NumProcs)
1461    OS << Target << "SubTypeKV, ";
1462  else
1463    OS << "0, ";
1464  OS << '\n'; OS.indent(22);
1465  OS << Target << "ProcSchedKV, "
1466     << Target << "WriteProcResTable, "
1467     << Target << "WriteLatencyTable, "
1468     << Target << "ReadAdvanceTable, ";
1469  if (SchedModels.hasItineraries()) {
1470    OS << '\n'; OS.indent(22);
1471    OS << Target << "Stages, "
1472       << Target << "OperandCycles, "
1473       << Target << "ForwardingPaths, ";
1474  } else
1475    OS << "0, 0, 0, ";
1476  OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1477
1478  OS << "} // End llvm namespace \n";
1479
1480  OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
1481
1482  OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
1483  OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
1484
1485  OS << "#include \"llvm/Support/Debug.h\"\n";
1486  OS << "#include \"llvm/Support/raw_ostream.h\"\n";
1487  ParseFeaturesFunction(OS, NumFeatures, NumProcs);
1488
1489  OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
1490
1491  // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
1492  OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
1493  OS << "#undef GET_SUBTARGETINFO_HEADER\n";
1494
1495  std::string ClassName = Target + "GenSubtargetInfo";
1496  OS << "namespace llvm {\n";
1497  OS << "class DFAPacketizer;\n";
1498  OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
1499     << "  explicit " << ClassName << "(StringRef TT, StringRef CPU, "
1500     << "StringRef FS);\n"
1501     << "public:\n"
1502     << "  unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI,"
1503     << " const TargetSchedModel *SchedModel) const;\n"
1504     << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
1505     << " const;\n"
1506     << "};\n";
1507  OS << "} // End llvm namespace \n";
1508
1509  OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
1510
1511  OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
1512  OS << "#undef GET_SUBTARGETINFO_CTOR\n";
1513
1514  OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n";
1515  OS << "namespace llvm {\n";
1516  OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
1517  OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
1518  OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
1519  OS << "extern const llvm::MCWriteProcResEntry "
1520     << Target << "WriteProcResTable[];\n";
1521  OS << "extern const llvm::MCWriteLatencyEntry "
1522     << Target << "WriteLatencyTable[];\n";
1523  OS << "extern const llvm::MCReadAdvanceEntry "
1524     << Target << "ReadAdvanceTable[];\n";
1525
1526  if (SchedModels.hasItineraries()) {
1527    OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
1528    OS << "extern const unsigned " << Target << "OperandCycles[];\n";
1529    OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
1530  }
1531
1532  OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
1533     << "StringRef FS)\n"
1534     << "  : TargetSubtargetInfo() {\n"
1535     << "  InitMCSubtargetInfo(TT, CPU, FS, ";
1536  if (NumFeatures)
1537    OS << Target << "FeatureKV, ";
1538  else
1539    OS << "0, ";
1540  if (NumProcs)
1541    OS << Target << "SubTypeKV, ";
1542  else
1543    OS << "0, ";
1544  OS << '\n'; OS.indent(22);
1545  OS << Target << "ProcSchedKV, "
1546     << Target << "WriteProcResTable, "
1547     << Target << "WriteLatencyTable, "
1548     << Target << "ReadAdvanceTable, ";
1549  OS << '\n'; OS.indent(22);
1550  if (SchedModels.hasItineraries()) {
1551    OS << Target << "Stages, "
1552       << Target << "OperandCycles, "
1553       << Target << "ForwardingPaths, ";
1554  } else
1555    OS << "0, 0, 0, ";
1556  OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1557
1558  EmitSchedModelHelpers(ClassName, OS);
1559
1560  OS << "} // End llvm namespace \n";
1561
1562  OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
1563}
1564
1565namespace llvm {
1566
1567void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
1568  CodeGenTarget CGTarget(RK);
1569  SubtargetEmitter(RK, CGTarget).run(OS);
1570}
1571
1572} // End llvm namespace
1573