1//===-- AMDILDeviceInfo.h - Constants for describing devices --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9#ifndef _AMDILDEVICEINFO_H_
10#define _AMDILDEVICEINFO_H_
11
12
13#include <string>
14
15namespace llvm
16{
17  class AMDGPUDevice;
18  class AMDGPUSubtarget;
19  namespace AMDGPUDeviceInfo
20  {
21    // Each Capabilities can be executed using a hardware instruction,
22    // emulated with a sequence of software instructions, or not
23    // supported at all.
24    enum ExecutionMode {
25      Unsupported = 0, // Unsupported feature on the card(Default value)
26      Software, // This is the execution mode that is set if the
27      // feature is emulated in software
28      Hardware  // This execution mode is set if the feature exists
29        // natively in hardware
30    };
31
32    // Any changes to this needs to have a corresponding update to the
33    // twiki page GPUMetadataABI
34    enum Caps {
35      HalfOps          = 0x1,  // Half float is supported or not.
36      DoubleOps        = 0x2,  // Double is supported or not.
37      ByteOps          = 0x3,  // Byte(char) is support or not.
38      ShortOps         = 0x4,  // Short is supported or not.
39      LongOps          = 0x5,  // Long is supported or not.
40      Images           = 0x6,  // Images are supported or not.
41      ByteStores       = 0x7,  // ByteStores available(!HD4XXX).
42      ConstantMem      = 0x8,  // Constant/CB memory.
43      LocalMem         = 0x9,  // Local/LDS memory.
44      PrivateMem       = 0xA,  // Scratch/Private/Stack memory.
45      RegionMem        = 0xB,  // OCL GDS Memory Extension.
46      FMA              = 0xC,  // Use HW FMA or SW FMA.
47      ArenaSegment     = 0xD,  // Use for Arena UAV per pointer 12-1023.
48      MultiUAV         = 0xE,  // Use for UAV per Pointer 0-7.
49      Reserved0        = 0xF,  // ReservedFlag
50      NoAlias          = 0x10, // Cached loads.
51      Signed24BitOps   = 0x11, // Peephole Optimization.
52      // Debug mode implies that no hardware features or optimizations
53      // are performned and that all memory access go through a single
54      // uav(Arena on HD5XXX/HD6XXX and Raw on HD4XXX).
55      Debug            = 0x12, // Debug mode is enabled.
56      CachedMem        = 0x13, // Cached mem is available or not.
57      BarrierDetect    = 0x14, // Detect duplicate barriers.
58      Reserved1        = 0x15, // Reserved flag
59      ByteLDSOps       = 0x16, // Flag to specify if byte LDS ops are available.
60      ArenaVectors     = 0x17, // Flag to specify if vector loads from arena work.
61      TmrReg           = 0x18, // Flag to specify if Tmr register is supported.
62      NoInline         = 0x19, // Flag to specify that no inlining should occur.
63      MacroDB          = 0x1A, // Flag to specify that backend handles macrodb.
64      HW64BitDivMod    = 0x1B, // Flag for backend to generate 64bit div/mod.
65      ArenaUAV         = 0x1C, // Flag to specify that arena uav is supported.
66      PrivateUAV       = 0x1D, // Flag to specify that private memory uses uav's.
67      // If more capabilities are required, then
68      // this number needs to be increased.
69      // All capabilities must come before this
70      // number.
71      MaxNumberCapabilities = 0x20
72    };
73    // These have to be in order with the older generations
74    // having the lower number enumerations.
75    enum Generation {
76      HD4XXX = 0, // 7XX based devices.
77      HD5XXX, // Evergreen based devices.
78      HD6XXX, // NI/Evergreen+ based devices.
79      HD7XXX,
80      HDTEST, // Experimental feature testing device.
81      HDNUMGEN
82    };
83
84
85  AMDGPUDevice*
86    getDeviceFromName(const std::string &name, AMDGPUSubtarget *ptr,
87                      bool is64bit = false, bool is64on32bit = false);
88  } // namespace AMDILDeviceInfo
89} // namespace llvm
90#endif // _AMDILDEVICEINFO_H_
91