Lines Matching refs:ZERO
525 ZERO,
687 gpr = ZERO;
694 gpr = ZERO;
763 GpuRegister gpr = ZERO;
895 // ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
896 blocked_core_registers_[ZERO] = true;
1070 GpuRegister rhs_reg = ZERO;
1177 GpuRegister rhs_reg = ZERO;
1710 GpuRegister rhs = ZERO;
1860 __ Move(out, ZERO);
1864 __ Subu(out, ZERO, dividend);
1867 __ Dsubu(out, ZERO, dividend);
1901 __ Subu(out, ZERO, out);
1923 __ Dsubu(out, ZERO, out);
2247 GpuRegister rhs_reg = ZERO;
2276 __ Sltu(dst, ZERO, dst);
2382 GpuRegister rhs_reg = ZERO;
2869 __ Move(out, ZERO);
3260 __ StoreToOffset(kStoreWord, ZERO, TR, GetExceptionTlsOffset());
3407 __ Subu(dst, ZERO, src);
3409 __ Dsubu(dst, ZERO, src);
3496 __ Nor(dst, src, ZERO);
3535 __ Lw(ZERO, obj.AsRegister<GpuRegister>(), 0);