Cross Reference: /art/compiler/utils/arm/assembler

Lines Matching refs:rd
56 bool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
65 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so,
67   EmitType01(cond, so.type(), AND, set_cc, rn, rd, so);
71 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so,
73   EmitType01(cond, so.type(), EOR, set_cc, rn, rd, so);
77 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so,
79   EmitType01(cond, so.type(), SUB, set_cc, rn, rd, so);
82 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so,
84   EmitType01(cond, so.type(), RSB, set_cc, rn, rd, so);
87 void Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so,
89   EmitType01(cond, so.type(), ADD, set_cc, rn, rd, so);
93 void Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so,
95   EmitType01(cond, so.type(), ADC, set_cc, rn, rd, so);
99 void Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so,
101   EmitType01(cond, so.type(), SBC, set_cc, rn, rd, so);
105 void Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so,
107   EmitType01(cond, so.type(), RSC, set_cc, rn, rd, so);
133 void Arm32Assembler::orr(Register rd, Register rn, const ShifterOperand& so,
135   EmitType01(cond, so.type(), ORR, set_cc, rn, rd, so);
139 void Arm32Assembler::orn(Register rd ATTRIBUTE_UNUSED,
148 void Arm32Assembler::mov(Register rd, const ShifterOperand& so,
150   EmitType01(cond, so.type(), MOV, set_cc, R0, rd, so);
154 void Arm32Assembler::bic(Register rd, Register rn, const ShifterOperand& so,
156   EmitType01(cond, so.type(), BIC, set_cc, rn, rd, so);
160 void Arm32Assembler::mvn(Register rd, const ShifterOperand& so,
162   EmitType01(cond, so.type(), MVN, set_cc, R0, rd, so);
166 void Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
167   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
168   EmitMulOp(cond, 0, R0, rd, rn, rm);
172 void Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra,
174   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
175   EmitMulOp(cond, B21, ra, rd, rn, rm);
179 void Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra,
181   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
182   EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
188   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
195   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
200 void Arm32Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
201   CHECK_NE(rd, kNoRegister);
209       (static_cast<int32_t>(rd) << 16) |
216 void Arm32Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
217   CHECK_NE(rd, kNoRegister);
225       (static_cast<int32_t>(rd) << 16) |
232 void Arm32Assembler::sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) {
233   CHECK_NE(rd, kNoRegister);
243       (static_cast<uint32_t>(rd) << 12) |
251 void Arm32Assembler::ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) {
252   CHECK_NE(rd, kNoRegister);
262       (static_cast<uint32_t>(rd) << 12) |
270 void Arm32Assembler::ldr(Register rd, const Address& ad, Condition cond) {
271   EmitMemOp(cond, true, false, rd, ad);
275 void Arm32Assembler::str(Register rd, const Address& ad, Condition cond) {
276   EmitMemOp(cond, false, false, rd, ad);
280 void Arm32Assembler::ldrb(Register rd, const Address& ad, Condition cond) {
281   EmitMemOp(cond, true, true, rd, ad);
285 void Arm32Assembler::strb(Register rd, const Address& ad, Condition cond) {
286   EmitMemOp(cond, false, true, rd, ad);
290 void Arm32Assembler::ldrh(Register rd, const Address& ad, Condition cond) {
291   EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
295 void Arm32Assembler::strh(Register rd, const Address& ad, Condition cond) {
296   EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
300 void Arm32Assembler::ldrsb(Register rd, const Address& ad, Condition cond) {
301   EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
305 void Arm32Assembler::ldrsh(Register rd, const Address& ad, Condition cond) {
306   EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
310 void Arm32Assembler::ldrd(Register rd, const Address& ad, Condition cond) {
311   CHECK_EQ(rd % 2, 0);
312   EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad);
316 void Arm32Assembler::strd(Register rd, const Address& ad, Condition cond) {
317   CHECK_EQ(rd % 2, 0);
318   EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad);
578                                 Register rd,
580   CHECK_NE(rd, kNoRegister);
587                      static_cast<int32_t>(rd) << kRdShift |
605                                Register rd,
607   CHECK_NE(rd, kNoRegister);
625          (static_cast<int32_t>(rd) << kRdShift) |
634         (static_cast<int32_t>(rd) << kRdShift) |
643                                            Register rd,
645   CHECK_NE(rd, kNoRegister);
651                      (static_cast<int32_t>(rd) << kRdShift) |
676                                         Register rd,
683                      static_cast<int32_t>(rd) << kRdShift |
693                                        Register rd,
700                      static_cast<int32_t>(rd) << kRdShift |
721 void Arm32Assembler::clz(Register rd, Register rm, Condition cond) {
722   CHECK_NE(rd, kNoRegister);
725   CHECK_NE(rd, PC);
729                      (static_cast<int32_t>(rd) << kRdShift) |
735 void Arm32Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
739                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
744 void Arm32Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
748                      static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
767 void Arm32Assembler::EmitReverseBytes(Register rd, Register rm, Condition cond,
769   CHECK_NE(rd, kNoRegister);
772   CHECK_NE(rd, PC);
775   int32_t encoding = (static_cast<int32_t>(rd) << kRdShift) |
782 void Arm32Assembler::rbit(Register rd, Register rm, Condition cond) {
783   CHECK_NE(rd, kNoRegister);
786   CHECK_NE(rd, PC);
790                      (static_cast<int32_t>(rd) << kRdShift) |
796 void Arm32Assembler::rev(Register rd, Register rm, Condition cond) {
797   EmitReverseBytes(rd, rm, cond, 0b011, 0b001);
801 void Arm32Assembler::rev16(Register rd, Register rm, Condition cond) {
802   EmitReverseBytes(rd, rm, cond, 0b011, 0b101);
806 void Arm32Assembler::revsh(Register rd, Register rm, Condition cond) {
807   EmitReverseBytes(rd, rm, cond, 0b111, 0b101);
812                                Register rd, Register rn,
814   CHECK_NE(rd, kNoRegister);
822       (static_cast<int32_t>(rd) << kRdShift) |
864 void Arm32Assembler::strex(Register rd,
869   CHECK_NE(rd, kNoRegister);
876                      (static_cast<int32_t>(rd) << kStrExRdShift) |
882 void Arm32Assembler::strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) {
883   CHECK_NE(rd, kNoRegister);
888   CHECK_NE(rd, rt);
889   CHECK_NE(rd, rt2);
898       static_cast<uint32_t>(rd) << 12 |
1201 void Arm32Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm,
1204   mov(rd, ShifterOperand(rm, LSL, shift_imm), cond, set_cc);
1208 void Arm32Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm,
1212   mov(rd, ShifterOperand(rm, LSR, shift_imm), cond, set_cc);
1216 void Arm32Assembler::Asr(Register rd, Register rm, uint32_t shift_imm,
1220   mov(rd, ShifterOperand(rm, ASR, shift_imm), cond, set_cc);
1224 void Arm32Assembler::Ror(Register rd, Register rm, uint32_t shift_imm,
1227   mov(rd, ShifterOperand(rm, ROR, shift_imm), cond, set_cc);
1230 void Arm32Assembler::Rrx(Register rd, Register rm, Condition cond, SetCc set_cc) {
1231   mov(rd, ShifterOperand(rm, ROR, 0), cond, set_cc);
1235 void Arm32Assembler::Lsl(Register rd, Register rm, Register rn,
1237   mov(rd, ShifterOperand(rm, LSL, rn), cond, set_cc);
1241 void Arm32Assembler::Lsr(Register rd, Register rm, Register rn,
1243   mov(rd, ShifterOperand(rm, LSR, rn), cond, set_cc);
1247 void Arm32Assembler::Asr(Register rd, Register rm, Register rn,
1249   mov(rd, ShifterOperand(rm, ASR, rn), cond, set_cc);
1253 void Arm32Assembler::Ror(Register rd, Register rm, Register rn,
1255   mov(rd, ShifterOperand(rm, ROR, rn), cond, set_cc);
1302 void Arm32Assembler::Push(Register rd, Condition cond) {
1303   str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond);
1307 void Arm32Assembler::Pop(Register rd, Condition cond) {
1308   ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond);
1322 void Arm32Assembler::Mov(Register rd, Register rm, Condition cond) {
1323   if (rd != rm) {
1324     mov(rd, ShifterOperand(rm), cond);
1398 void Arm32Assembler::AddConstant(Register rd, Register rn, int32_t value,
1401     if (rd != rn) {
1402       mov(rd, ShifterOperand(rn), cond, set_cc);
1411     add(rd, rn, shifter_op, cond, set_cc);
1413     sub(rd, rn, shifter_op, cond, set_cc);
1418       add(rd, rn, ShifterOperand(IP), cond, set_cc);
1421       sub(rd, rn, ShifterOperand(IP), cond, set_cc);
1428       add(rd, rn, ShifterOperand(IP), cond, set_cc);
1449 void Arm32Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
1452     mov(rd, shifter_op, cond);
1454     mvn(rd, shifter_op, cond);
1456     movw(rd, Low16Bits(value), cond);
1459       movt(rd, value_high, cond);