Lines Matching defs:opcode
515 Opcode opcode,
523 switch (opcode) {
1176 Opcode opcode,
1186 if ((opcode == ADD || opcode == SUB) && rn == SP && so.IsImmediate() && set_cc != kCcSet) {
1192 } else if (!IsHighRegister(rd) && opcode == ADD) {
1200 (opcode == CMP) ||
1201 (opcode == MOV && set_cc != kCcSet) ||
1202 ((opcode == ADD) && (rn == rd) && set_cc != kCcSet);
1209 // There are high register instructions available for this opcode.
1229 switch (opcode) {
1249 if (opcode == RSB) {
1257 if (opcode == ADD || opcode == SUB) {
1269 if (!(opcode == ADD || opcode == SUB || opcode == MOV || opcode == CMP)) {
1271 } else if (opcode != CMP && ((cond == AL) ? set_cc == kCcKeep : set_cc == kCcSet)) {
1274 // For ADD and SUB allow also negative 8-bit immediate as we will emit the oposite opcode.
1276 (opcode == MOV || opcode == CMP || !IsUint<8>(-so.GetImmediate()))) {
1285 if (opcode != MOV) {
1299 switch (opcode) {
1339 Opcode opcode,
1345 switch (opcode) {
1368 LOG(FATAL) << "Invalid thumb2 opcode " << opcode;
1375 if ((opcode == SUB || opcode == ADD) && (so.GetImmediate() < (1u << 12)) &&
1378 if (opcode == SUB) {
1380 } else if (opcode == ADD) {
1426 Opcode opcode,
1431 if (opcode == ADD || opcode == SUB) {
1432 Emit16BitAddSub(cond, opcode, set_cc, rn, rd, so);
1445 if (opcode == MOV && so.IsRegister() && so.IsShift()) {
1485 switch (opcode) {
1530 switch (opcode) {
1553 // Put the top bit of rd into the bottom bit of the opcode.
1581 // Put the top bit of rd into the bottom bit of the opcode.
1595 LOG(FATAL) << "Invalid thumb1 opcode " << opcode;
1601 LOG(FATAL) << "Invalid thumb1 opcode " << opcode;
1617 Opcode opcode,
1636 opcode = (opcode == ADD) ? SUB : ADD;
1642 switch (opcode) {
1762 LOG(FATAL) << "This opcode is not an ADD or SUB: " << opcode;
1777 Opcode opcode,
1785 if (Is32BitDataProcessing(cond, opcode, set_cc, rn, rd, so)) {
1786 Emit32BitDataProcessing(cond, opcode, set_cc, rn, rd, so);
1788 Emit16BitDataProcessing(cond, opcode, set_cc, rn, rd, so);
1801 uint16_t opcode = 0;
1803 case LSL: opcode = 0U /* 0b00 */; break;
1804 case LSR: opcode = 1U /* 0b01 */; break;
1805 case ASR: opcode = 2U /* 0b10 */; break;
1806 case ROR: opcode = 3U /* 0b11 */; break;
1807 case RRX: opcode = 3U /* 0b11 */; amount = 0; break;
1809 LOG(FATAL) << "Unsupported thumb2 shift opcode";
1818 static_cast<int16_t>(rd) << 8 | opcode << 4;
1822 uint16_t opcode = 0;
1824 case LSL: opcode = 0U /* 0b00 */; break;
1825 case LSR: opcode = 1U /* 0b01 */; break;
1826 case ASR: opcode = 2U /* 0b10 */; break;
1828 LOG(FATAL) << "Unsupported thumb2 shift opcode";
1831 int16_t encoding = opcode << 11 | amount << 6 | static_cast<int16_t>(rm) << 3 |
1851 uint16_t opcode = 0;
1853 case LSL: opcode = 0U /* 0b00 */; break;
1854 case LSR: opcode = 1U /* 0b01 */; break;
1855 case ASR: opcode = 2U /* 0b10 */; break;
1856 case ROR: opcode = 3U /* 0b11 */; break;
1858 LOG(FATAL) << "Unsupported thumb2 shift opcode";
1865 static_cast<int16_t>(rd) << 8 | opcode << 21;
1868 uint16_t opcode = 0;
1870 case LSL: opcode = 2U /* 0b0010 */; break;
1871 case LSR: opcode = 3U /* 0b0011 */; break;
1872 case ASR: opcode = 4U /* 0b0100 */; break;
1873 case ROR: opcode = 7U /* 0b0111 */; break;
1875 LOG(FATAL) << "Unsupported thumb2 shift opcode";
1878 int16_t encoding = B14 | opcode << 6 | static_cast<int16_t>(rm) << 3 |
3044 void Thumb2Assembler::EmitVFPsss(Condition cond, int32_t opcode,
3051 B27 | B26 | B25 | B11 | B9 | opcode |
3062 void Thumb2Assembler::EmitVFPddd(Condition cond, int32_t opcode,
3069 B27 | B26 | B25 | B11 | B9 | B8 | opcode |
3080 void Thumb2Assembler::EmitVFPsd(Condition cond, int32_t opcode,
3086 B27 | B26 | B25 | B11 | B9 | opcode |
3095 void Thumb2Assembler::EmitVFPds(Condition cond, int32_t opcode,
3101 B27 | B26 | B25 | B11 | B9 | opcode |