Cross Reference: /art/compiler/utils/arm64/assembler

Lines Matching refs:dst
293   Arm64ManagedRegister dst = m_dst.AsArm64();
294   CHECK(dst.IsXRegister()) << dst;
295   LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), SP, offs.Int32Value());
300   Arm64ManagedRegister dst = m_dst.AsArm64();
302   CHECK(dst.IsXRegister() && base.IsXRegister());
303   LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), base.AsXRegister(),
306     WRegister ref_reg = dst.AsOverlappingWRegister();
312   Arm64ManagedRegister dst = m_dst.AsArm64();
314   CHECK(dst.IsXRegister() && base.IsXRegister());
315   // Remove dst and base form the temp list - higher level API uses IP1, IP0.
317   temps.Exclude(reg_x(dst.AsXRegister()), reg_x(base.AsXRegister()));
318   ___ Ldr(reg_x(dst.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value()));
322   Arm64ManagedRegister dst = m_dst.AsArm64();
323   CHECK(dst.IsXRegister()) << dst;
324   LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value());
329   Arm64ManagedRegister dst = m_dst.AsArm64();
331   if (!dst.Equals(src)) {
332     if (dst.IsXRegister()) {
335         ___ Mov(reg_w(dst.AsOverlappingWRegister()), reg_w(src.AsWRegister()));
338           ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsXRegister()));
340           ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsOverlappingXRegister()));
343     } else if (dst.IsWRegister()) {
345       ___ Mov(reg_w(dst.AsWRegister()), reg_w(src.AsWRegister()));
346     } else if (dst.IsSRegister()) {
348       ___ Fmov(reg_s(dst.AsSRegister()), reg_s(src.AsSRegister()));
350       CHECK(dst.IsDRegister()) << dst;
352       ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister()));
439 void Arm64Assembler::Copy(FrameOffset /*dst*/, FrameOffset /*src_base*/, Offset /*src_offset*/,
474 void Arm64Assembler::Copy(FrameOffset /*dst*/, Offset /*dest_offset*/,