Lines Matching defs:opcode
91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,
96 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
109 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,
122 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) {
134 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
141 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) {
144 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
150 void Mips64Assembler::EmitI26(int opcode, uint32_t imm26) {
152 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift | imm26;
156 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd,
161 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |
170 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) {
172 uint32_t encoding = static_cast<uint32_t>(opcode) << kOpcodeShift |