Cross Reference: /art/compiler/utils/mips64/assembler

Lines Matching defs:rs
91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,
93   CHECK_NE(rs, kNoGpuRegister);
97                       static_cast<uint32_t>(rs) << kRsShift |
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
107   CHECK_NE(rs, kNoGpuRegister);
110                       static_cast<uint32_t>(rs) << kRsShift |
131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) {
132   CHECK_NE(rs, kNoGpuRegister);
135                       static_cast<uint32_t>(rs) << kRsShift |
141 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) {
142   CHECK_NE(rs, kNoGpuRegister);
145                       static_cast<uint32_t>(rs) << kRsShift |
179 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
180   EmitR(0, rs, rt, rd, 0, 0x21);
183 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
184   EmitI(0x9, rs, rt, imm16);
187 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
188   EmitR(0, rs, rt, rd, 0, 0x2d);
191 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
192   EmitI(0x19, rs, rt, imm16);
195 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
196   EmitR(0, rs, rt, rd, 0, 0x23);
199 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
200   EmitR(0, rs, rt, rd, 0, 0x2f);
203 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
204   EmitR(0, rs, rt, rd, 2, 0x18);
207 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
208   EmitR(0, rs, rt, rd, 3, 0x18);
211 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
212   EmitR(0, rs, rt, rd, 2, 0x1a);
215 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
216   EmitR(0, rs, rt, rd, 3, 0x1a);
219 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
220   EmitR(0, rs, rt, rd, 2, 0x1b);
223 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
224   EmitR(0, rs, rt, rd, 3, 0x1b);
227 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
228   EmitR(0, rs, rt, rd, 2, 0x1c);
231 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
232   EmitR(0, rs, rt, rd, 3, 0x1c);
235 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
236   EmitR(0, rs, rt, rd, 2, 0x1e);
239 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
240   EmitR(0, rs, rt, rd, 3, 0x1e);
243 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
244   EmitR(0, rs, rt, rd, 2, 0x1f);
247 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
248   EmitR(0, rs, rt, rd, 3, 0x1f);
251 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
252   EmitR(0, rs, rt, rd, 0, 0x24);
255 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
256   EmitI(0xc, rs, rt, imm16);
259 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
260   EmitR(0, rs, rt, rd, 0, 0x25);
263 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
264   EmitI(0xd, rs, rt, imm16);
267 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
268   EmitR(0, rs, rt, rd, 0, 0x26);
271 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
272   EmitI(0xe, rs, rt, imm16);
275 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
276   EmitR(0, rs, rt, rd, 0, 0x27);
303 void Mips64Assembler::Dext(GpuRegister rt, GpuRegister rs, int pos, int size) {
306   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(size - 1), pos, 0x3);
309 void Mips64Assembler::Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) {
313   EmitR(0x1f, rs, rt, static_cast<GpuRegister>(pos + size - 33), pos - 32, 0x6);
356 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
357   EmitR(0, rs, rt, rd, 0, 0x04);
360 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
361   EmitR(0, rs, rt, rd, 1, 0x06);
364 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
365   EmitR(0, rs, rt, rd, 0, 0x06);
368 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
369   EmitR(0, rs, rt, rd, 0, 0x07);
404 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
405   EmitR(0, rs, rt, rd, 0, 0x14);
408 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
409   EmitR(0, rs, rt, rd, 0, 0x16);
412 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
413   EmitR(0, rs, rt, rd, 1, 0x16);
416 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
417   EmitR(0, rs, rt, rd, 0, 0x17);
420 void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
421   EmitI(0x20, rs, rt, imm16);
424 void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
425   EmitI(0x21, rs, rt, imm16);
428 void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
429   EmitI(0x23, rs, rt, imm16);
432 void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
433   EmitI(0x37, rs, rt, imm16);
436 void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
437   EmitI(0x24, rs, rt, imm16);
440 void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
441   EmitI(0x25, rs, rt, imm16);
444 void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
445   EmitI(0x27, rs, rt, imm16);
452 void Mips64Assembler::Dahi(GpuRegister rs, uint16_t imm16) {
453   EmitI(1, rs, static_cast<GpuRegister>(6), imm16);
456 void Mips64Assembler::Dati(GpuRegister rs, uint16_t imm16) {
457   EmitI(1, rs, static_cast<GpuRegister>(0x1e), imm16);
465 void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
466   EmitI(0x28, rs, rt, imm16);
469 void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
470   EmitI(0x29, rs, rt, imm16);
473 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
474   EmitI(0x2b, rs, rt, imm16);
477 void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
478   EmitI(0x3f, rs, rt, imm16);
481 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
482   EmitR(0, rs, rt, rd, 0, 0x2a);
485 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
486   EmitR(0, rs, rt, rd, 0, 0x2b);
489 void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
490   EmitI(0xa, rs, rt, imm16);
493 void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
494   EmitI(0xb, rs, rt, imm16);
497 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
498   EmitR(0, rs, rt, rd, 0, 0x35);
501 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
502   EmitR(0, rs, rt, rd, 0, 0x37);
505 void Mips64Assembler::Clz(GpuRegister rd, GpuRegister rs) {
506   EmitRsd(0, rs, rd, 0x01, 0x10);
509 void Mips64Assembler::Clo(GpuRegister rd, GpuRegister rs) {
510   EmitRsd(0, rs, rd, 0x01, 0x11);
513 void Mips64Assembler::Dclz(GpuRegister rd, GpuRegister rs) {
514   EmitRsd(0, rs, rd, 0x01, 0x12);
517 void Mips64Assembler::Dclo(GpuRegister rd, GpuRegister rs) {
518   EmitRsd(0, rs, rd, 0x01, 0x13);
521 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) {
522   EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);
525 void Mips64Assembler::Jalr(GpuRegister rs) {
526   Jalr(RA, rs);
529 void Mips64Assembler::Jr(GpuRegister rs) {
530   Jalr(ZERO, rs);
533 void Mips64Assembler::Auipc(GpuRegister rs, uint16_t imm16) {
534   EmitI(0x3B, rs, static_cast<GpuRegister>(0x1E), imm16);
537 void Mips64Assembler::Addiupc(GpuRegister rs, uint32_t imm19) {
539   EmitI21(0x3B, rs, imm19);
554 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
555   CHECK_NE(rs, ZERO);
557   CHECK_NE(rs, rt);
558   EmitI(0x17, rs, rt, imm16);
571 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
572   CHECK_NE(rs, ZERO);
574   CHECK_NE(rs, rt);
575   EmitI(0x16, rs, rt, imm16);
588 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
589   CHECK_NE(rs, ZERO);
591   CHECK_NE(rs, rt);
592   EmitI(0x7, rs, rt, imm16);
595 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
596   CHECK_NE(rs, ZERO);
598   CHECK_NE(rs, rt);
599   EmitI(0x6, rs, rt, imm16);
602 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
603   CHECK_NE(rs, ZERO);
605   CHECK_NE(rs, rt);
606   EmitI(0x8, std::min(rs, rt), std::max(rs, rt), imm16);
609 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
610   CHECK_NE(rs, ZERO);
612   CHECK_NE(rs, rt);
613   EmitI(0x18, std::min(rs, rt), std::max(rs, rt), imm16);
616 void Mips64Assembler::Beqzc(GpuRegister rs, uint32_t imm21) {
617   CHECK_NE(rs, ZERO);
618   EmitI21(0x36, rs, imm21);
621 void Mips64Assembler::Bnezc(GpuRegister rs, uint32_t imm21) {
622   CHECK_NE(rs, ZERO);
623   EmitI21(0x3E, rs, imm21);
635                                  GpuRegister rs,
640       Bltc(rs, rt, imm16_21);
643       Bgec(rs, rt, imm16_21);
646       Bgec(rt, rs, imm16_21);
649       Bltc(rt, rs, imm16_21);
653       Bltzc(rs, imm16_21);
657       Bgezc(rs, imm16_21);
661       Blezc(rs, imm16_21);
665       Bgtzc(rs, imm16_21);
668       Beqc(rs, rt, imm16_21);
671       Bnec(rs, rt, imm16_21);
675       Beqzc(rs, imm16_21);
679       Bnezc(rs, imm16_21);
682       Bltuc(rs, rt, imm16_21);
685       Bgeuc(rs, rt, imm16_21);
689       Bc1eqz(static_cast<FpuRegister>(rs), imm16_21);
693       Bc1nez(static_cast<FpuRegister>(rs), imm16_21);
997 void Mips64Assembler::Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
998   EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16);
1001 void Mips64Assembler::Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
1002   EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16);
1005 void Mips64Assembler::Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
1006   EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16);
1009 void Mips64Assembler::Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) {
1010   EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16);
1023 void Mips64Assembler::Move(GpuRegister rd, GpuRegister rs) {
1024   Or(rd, rs, ZERO);
1031 void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) {
1032   Nor(rd, rs, ZERO);
1161 void Mips64Assembler::Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) {
1163     Daddiu(rt, rs, value);
1166     Daddu(rt, rs, rtmp);
1747 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label) {
1748   Bcond(label, kCondLT, rs, rt);
1759 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label) {
1760   Bcond(label, kCondGE, rs, rt);
1771 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) {
1772   Bcond(label, kCondLTU, rs, rt);
1775 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) {
1776   Bcond(label, kCondGEU, rs, rt);
1779 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label) {
1780   Bcond(label, kCondEQ, rs, rt);
1783 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label) {
1784   Bcond(label, kCondNE, rs, rt);
1787 void Mips64Assembler::Beqzc(GpuRegister rs, Mips64Label* label) {
1788   Bcond(label, kCondEQZ, rs);
1791 void Mips64Assembler::Bnezc(GpuRegister rs, Mips64Label* label) {
1792   Bcond(label, kCondNEZ, rs);