Cross Reference: /art/compiler/utils/mips64/assembler

Lines Matching refs:rd
91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,
95   CHECK_NE(rd, kNoGpuRegister);
99                       static_cast<uint32_t>(rd) << kRdShift |
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,
108   CHECK_NE(rd, kNoGpuRegister);
112                       static_cast<uint32_t>(rd) << kRdShift |
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,
121   CHECK_NE(rd, kNoGpuRegister);
125                       static_cast<uint32_t>(rd) << kRdShift |
179 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
180   EmitR(0, rs, rt, rd, 0, 0x21);
187 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
188   EmitR(0, rs, rt, rd, 0, 0x2d);
195 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
196   EmitR(0, rs, rt, rd, 0, 0x23);
199 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
200   EmitR(0, rs, rt, rd, 0, 0x2f);
203 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
204   EmitR(0, rs, rt, rd, 2, 0x18);
207 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
208   EmitR(0, rs, rt, rd, 3, 0x18);
211 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
212   EmitR(0, rs, rt, rd, 2, 0x1a);
215 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
216   EmitR(0, rs, rt, rd, 3, 0x1a);
219 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
220   EmitR(0, rs, rt, rd, 2, 0x1b);
223 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
224   EmitR(0, rs, rt, rd, 3, 0x1b);
227 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
228   EmitR(0, rs, rt, rd, 2, 0x1c);
231 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
232   EmitR(0, rs, rt, rd, 3, 0x1c);
235 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
236   EmitR(0, rs, rt, rd, 2, 0x1e);
239 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
240   EmitR(0, rs, rt, rd, 3, 0x1e);
243 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
244   EmitR(0, rs, rt, rd, 2, 0x1f);
247 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
248   EmitR(0, rs, rt, rd, 3, 0x1f);
251 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
252   EmitR(0, rs, rt, rd, 0, 0x24);
259 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
260   EmitR(0, rs, rt, rd, 0, 0x25);
267 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
268   EmitR(0, rs, rt, rd, 0, 0x26);
275 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
276   EmitR(0, rs, rt, rd, 0, 0x27);
279 void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) {
280   EmitRtd(0x1f, rt, rd, 0x0, 0x20);
283 void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) {
284   EmitRtd(0x1f, rt, rd, 0x0, 0x24);
287 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) {
288   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x10, 0x20);
291 void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) {
292   EmitR(0x1f, static_cast<GpuRegister>(0), rt, rd, 0x18, 0x20);
295 void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) {
296   EmitRtd(0x1f, rt, rd, 0x2, 0x24);
299 void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) {
300   EmitRtd(0x1f, rt, rd, 0x5, 0x24);
316 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) {
317   EmitRtd(0x1f, rt, rd, 2, 0x20);
340 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) {
341   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
344 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {
345   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);
348 void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) {
349   EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x02);
352 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) {
353   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);
356 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
357   EmitR(0, rs, rt, rd, 0, 0x04);
360 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
361   EmitR(0, rs, rt, rd, 1, 0x06);
364 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
365   EmitR(0, rs, rt, rd, 0, 0x06);
368 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
369   EmitR(0, rs, rt, rd, 0, 0x07);
372 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) {
373   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38);
376 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) {
377   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3a);
380 void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) {
381   EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3a);
384 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) {
385   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3b);
388 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) {
389   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3c);
392 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) {
393   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3e);
396 void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) {
397   EmitR(0, static_cast<GpuRegister>(1), rt, rd, shamt, 0x3e);
400 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) {
401   EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x3f);
404 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
405   EmitR(0, rs, rt, rd, 0, 0x14);
408 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
409   EmitR(0, rs, rt, rd, 0, 0x16);
412 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
413   EmitR(0, rs, rt, rd, 1, 0x16);
416 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {
417   EmitR(0, rs, rt, rd, 0, 0x17);
481 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
482   EmitR(0, rs, rt, rd, 0, 0x2a);
485 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
486   EmitR(0, rs, rt, rd, 0, 0x2b);
497 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
498   EmitR(0, rs, rt, rd, 0, 0x35);
501 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
502   EmitR(0, rs, rt, rd, 0, 0x37);
505 void Mips64Assembler::Clz(GpuRegister rd, GpuRegister rs) {
506   EmitRsd(0, rs, rd, 0x01, 0x10);
509 void Mips64Assembler::Clo(GpuRegister rd, GpuRegister rs) {
510   EmitRsd(0, rs, rd, 0x01, 0x11);
513 void Mips64Assembler::Dclz(GpuRegister rd, GpuRegister rs) {
514   EmitRsd(0, rs, rd, 0x01, 0x12);
517 void Mips64Assembler::Dclo(GpuRegister rd, GpuRegister rs) {
518   EmitRsd(0, rs, rd, 0x01, 0x13);
521 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) {
522   EmitR(0, rs, static_cast<GpuRegister>(0), rd, 0, 0x09);
1023 void Mips64Assembler::Move(GpuRegister rd, GpuRegister rs) {
1024   Or(rd, rs, ZERO);
1027 void Mips64Assembler::Clear(GpuRegister rd) {
1028   Move(rd, ZERO);
1031 void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) {
1032   Nor(rd, rs, ZERO);
1035 void Mips64Assembler::LoadConst32(GpuRegister rd, int32_t value) {
1038     Ori(rd, ZERO, value);
1041     Addiu(rd, ZERO, value);
1043     Lui(rd, value >> 16);
1045       Ori(rd, rd, value);
1049 void Mips64Assembler::LoadConst64(GpuRegister rd, int64_t value) {
1054     Ori(rd, ZERO, value);
1056     Daddiu(rd, ZERO, value);
1058     Lui(rd, value >> 16);
1061     Lui(rd, value >> 16);
1062     Ori(rd, rd, value);
1064     Ori(rd, ZERO, value);
1065     Dahi(rd, value >> 32);
1067     Ori(rd, ZERO, value);
1068     Dati(rd, value >> 48);
1071     Lui(rd, value >> 16);
1072     Dahi(rd, (value >> 32) + bit31);
1074     Lui(rd, value >> 16);
1075     Dati(rd, (value >> 48) + bit31);
1078     Daddiu(rd, ZERO, -1);
1080       Dsrl(rd, rd, shift_cnt);
1082       Dsrl32(rd, rd, shift_cnt & 31);
1088       Ori(rd, ZERO, tmp);
1090         Dsll(rd, rd, shift_cnt);
1092         Dsll32(rd, rd, shift_cnt & 31);
1095       Daddiu(rd, ZERO, tmp);
1097         Dsll(rd, rd, shift_cnt);
1099         Dsll32(rd, rd, shift_cnt & 31);
1103       Lui(rd, tmp >> 16);
1104       Ori(rd, rd, tmp);
1106         Dsll(rd, rd, shift_cnt);
1108         Dsll32(rd, rd, shift_cnt & 31);
1114         Ori(rd, ZERO, tmp);
1116           Dsll(rd, rd, shift_cnt);
1118           Dsll32(rd, rd, shift_cnt & 31);
1120         Ori(rd, rd, value);
1122         Daddiu(rd, ZERO, tmp);
1124           Dsll(rd, rd, shift_cnt);
1126           Dsll32(rd, rd, shift_cnt & 31);
1128         Ori(rd, rd, value);
1134           Lui(rd, tmp2 >> 16);
1139             Ori(rd, rd, tmp2);
1141             Ori(rd, ZERO, tmp2);
1148           Dahi(rd, tmp2 >> 32);
1154           Dati(rd, tmp2 >> 48);