Cross Reference: /art/compiler/utils/mips64/assembler

Lines Matching refs:GpuRegister
122   void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
123   void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
124   void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
125   void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
126   void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
127   void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
129   void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
130   void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
131   void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
132   void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
133   void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
134   void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
135   void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
136   void Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
137   void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
138   void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
139   void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
140   void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
142   void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
143   void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
144   void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt);
145   void Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
146   void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
147   void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
148   void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
150   void Bitswap(GpuRegister rd, GpuRegister rt);
151   void Dbitswap(GpuRegister rd, GpuRegister rt);
152   void Seb(GpuRegister rd, GpuRegister rt);
153   void Seh(GpuRegister rd, GpuRegister rt);
154   void Dsbh(GpuRegister rd, GpuRegister rt);
155   void Dshd(GpuRegister rd, GpuRegister rt);
156   void Dext(GpuRegister rs, GpuRegister rt, int pos, int size);  // MIPS64
157   void Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size);  // MIPS64
158   void Wsbh(GpuRegister rd, GpuRegister rt);
159   void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
160   void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
161   void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
162   void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
164   void Sll(GpuRegister rd, GpuRegister rt, int shamt);
165   void Srl(GpuRegister rd, GpuRegister rt, int shamt);
166   void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
167   void Sra(GpuRegister rd, GpuRegister rt, int shamt);
168   void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
169   void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
170   void Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
171   void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs);
172   void Dsll(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
173   void Dsrl(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
174   void Drotr(GpuRegister rd, GpuRegister rt, int shamt);
175   void Dsra(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
176   void Dsll32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
177   void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
178   void Drotr32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
179   void Dsra32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
180   void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
181   void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
182   void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
183   void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
185   void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
186   void Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
187   void Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
188   void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
189   void Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
190   void Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
191   void Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
192   void Lui(GpuRegister rt, uint16_t imm16);
193   void Dahi(GpuRegister rs, uint16_t imm16);  // MIPS64
194   void Dati(GpuRegister rs, uint16_t imm16);  // MIPS64
197   void Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
198   void Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
199   void Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
200   void Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16);  // MIPS64
202   void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt);
203   void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
204   void Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16);
205   void Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
206   void Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt);
207   void Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt);
208   void Clz(GpuRegister rd, GpuRegister rs);
209   void Clo(GpuRegister rd, GpuRegister rs);
210   void Dclz(GpuRegister rd, GpuRegister rs);
211   void Dclo(GpuRegister rd, GpuRegister rs);
213   void Jalr(GpuRegister rd, GpuRegister rs);
214   void Jalr(GpuRegister rs);
215   void Jr(GpuRegister rs);
216   void Auipc(GpuRegister rs, uint16_t imm16);
217   void Addiupc(GpuRegister rs, uint32_t imm19);
219   void Jic(GpuRegister rt, uint16_t imm16);
220   void Jialc(GpuRegister rt, uint16_t imm16);
221   void Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
222   void Bltzc(GpuRegister rt, uint16_t imm16);
223   void Bgtzc(GpuRegister rt, uint16_t imm16);
224   void Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16);
225   void Bgezc(GpuRegister rt, uint16_t imm16);
226   void Blezc(GpuRegister rt, uint16_t imm16);
227   void Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
228   void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
229   void Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
230   void Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16);
231   void Beqzc(GpuRegister rs, uint32_t imm21);
232   void Bnezc(GpuRegister rs, uint32_t imm21);
306   void Mfc1(GpuRegister rt, FpuRegister fs);
307   void Mfhc1(GpuRegister rt, FpuRegister fs);
308   void Mtc1(GpuRegister rt, FpuRegister fs);
309   void Mthc1(GpuRegister rt, FpuRegister fs);
310   void Dmfc1(GpuRegister rt, FpuRegister fs);  // MIPS64
311   void Dmtc1(GpuRegister rt, FpuRegister fs);  // MIPS64
312   void Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
313   void Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
314   void Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
315   void Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16);
319   void Move(GpuRegister rd, GpuRegister rs);
320   void Clear(GpuRegister rd);
321   void Not(GpuRegister rd, GpuRegister rs);
324   void LoadConst32(GpuRegister rd, int32_t value);
325   void LoadConst64(GpuRegister rd, int64_t value);  // MIPS64
327   void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT);  // MIPS64
338   void Jialc(Mips64Label* label, GpuRegister indirect_reg);
339   void Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label);
340   void Bltzc(GpuRegister rt, Mips64Label* label);
341   void Bgtzc(GpuRegister rt, Mips64Label* label);
342   void Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label);
343   void Bgezc(GpuRegister rt, Mips64Label* label);
344   void Blezc(GpuRegister rt, Mips64Label* label);
345   void Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label);
346   void Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label);
347   void Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label);
348   void Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label);
349   void Beqzc(GpuRegister rs, Mips64Label* label);
350   void Bnezc(GpuRegister rs, Mips64Label* label);
354   void EmitLoad(ManagedRegister m_dst, GpuRegister src_register, int32_t src_offset, size_t size);
355   void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
356   void LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset);
357   void StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
358   void StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset);
569            GpuRegister lhs_reg,
570            GpuRegister rhs_reg = ZERO);
572     Branch(uint32_t location, uint32_t target, GpuRegister indirect_reg);
578     static bool IsNop(BranchCondition condition, GpuRegister lhs, GpuRegister rhs);
579     static bool IsUncond(BranchCondition condition, GpuRegister lhs, GpuRegister rhs);
585     GpuRegister GetLeftRegister() const;
586     GpuRegister GetRightRegister() const;
664     GpuRegister lhs_reg_;        // Left-hand side register in conditional branches or
666     GpuRegister rhs_reg_;        // Right-hand side register in conditional branches.
675   void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);
676   void EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct);
677   void EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct);
678   void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm);
679   void EmitI21(int opcode, GpuRegister rs, uint32_t imm21);
683   void EmitBcondc(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint32_t imm16_21);
688              GpuRegister lhs,
689              GpuRegister rhs = ZERO);
690   void Call(Mips64Label* label, GpuRegister indirect_reg);