Cross Reference: /art/compiler/utils/mips64/assembler

Lines Matching refs:rd
122   void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
124   void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
126   void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
127   void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
129   void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
130   void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
131   void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
132   void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
133   void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
134   void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
135   void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
136   void Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
137   void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
138   void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
139   void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
140   void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
142   void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
144   void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt);
146   void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
148   void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
150   void Bitswap(GpuRegister rd, GpuRegister rt);
151   void Dbitswap(GpuRegister rd, GpuRegister rt);
152   void Seb(GpuRegister rd, GpuRegister rt);
153   void Seh(GpuRegister rd, GpuRegister rt);
154   void Dsbh(GpuRegister rd, GpuRegister rt);
155   void Dshd(GpuRegister rd, GpuRegister rt);
158   void Wsbh(GpuRegister rd, GpuRegister rt);
164   void Sll(GpuRegister rd, GpuRegister rt, int shamt);
165   void Srl(GpuRegister rd, GpuRegister rt, int shamt);
166   void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
167   void Sra(GpuRegister rd, GpuRegister rt, int shamt);
168   void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
169   void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
170   void Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
171   void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs);
172   void Dsll(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
173   void Dsrl(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
174   void Drotr(GpuRegister rd, GpuRegister rt, int shamt);
175   void Dsra(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
176   void Dsll32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
177   void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
178   void Drotr32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
179   void Dsra32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
180   void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
181   void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
182   void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
183   void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
202   void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt);
203   void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
206   void Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt);
207   void Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt);
208   void Clz(GpuRegister rd, GpuRegister rs);
209   void Clo(GpuRegister rd, GpuRegister rs);
210   void Dclz(GpuRegister rd, GpuRegister rs);
211   void Dclo(GpuRegister rd, GpuRegister rs);
213   void Jalr(GpuRegister rd, GpuRegister rs);
319   void Move(GpuRegister rd, GpuRegister rs);
320   void Clear(GpuRegister rd);
321   void Not(GpuRegister rd, GpuRegister rs);
324   void LoadConst32(GpuRegister rd, int32_t value);
325   void LoadConst64(GpuRegister rd, int64_t value);  // MIPS64
675   void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);
676   void EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct);
677   void EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct);