Lines Matching refs:SU
207 /// the exit SU to the register defs and use list. This is because we want to
245 /// MO is an operand of SU's instruction that defines a physical register. Add
246 /// data dependencies from SU to any uses of the physical register.
247 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
248 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
259 SUnit *UseSU = I->SU;
260 if (UseSU == SU)
269 Dep = SDep(SU, SDep::Artificial);
273 SU->hasPhysRegDefs = true;
274 Dep = SDep(SU, SDep::Data, *Alias);
278 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
281 ST.adjustSchedDependency(SU, UseSU, Dep);
290 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
291 MachineInstr *MI = SU->getInstr();
306 SUnit *DefSU = I->SU;
309 if (DefSU != SU &&
313 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
315 SDep Dep(SU, Kind, /*Reg=*/*Alias);
325 SU->hasPhysRegUses = true;
329 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
334 addPhysRegDataDeps(SU, OperIdx);
343 } else if (SU->isCall) {
354 if (!I->SU->isCall)
361 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
385 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
386 MachineInstr *MI = SU->getInstr();
423 SUnit *UseSU = I->SU;
425 SDep Dep(SU, SDep::Data, Reg);
428 ST.adjustSchedDependency(SU, UseSU, Dep);
460 SUnit *DefSU = V2SU.SU;
466 if (DefSU == SU)
468 SDep Dep(SU, SDep::Output, Reg);
479 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, V2SU.SU));
480 V2SU.SU = SU;
485 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
494 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
495 const MachineInstr *MI = SU->getInstr();
501 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
510 if (V2SU.SU == SU)
513 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
681 /// This function assumes that "downward" from SU there exist
683 /// checks whether SU can be aliasing any node dominated
686 const DataLayout &DL, SUnit *SU, SUnit *ExitSU,
689 if (!SU)
697 if (SU == *I)
699 if (MIsNeedChainEdge(AA, MFI, DL, SU->getInstr(), (*I)->getInstr())) {
700 SDep Dep(SU, SDep::MayAliasMem);
710 iterateChainSucc(AA, MFI, DL, SU, J->getSUnit(), ExitSU, &Depth,
716 /// otherwise remember the rejected SU.
733 DEBUG(dbgs() << "\tReject chain dep between SU("
734 << SUa->NodeNum << ") and SU("
760 SUnit *SU = newSUnit(MI);
761 MISUnitMap[MI] = SU;
763 SU->isCall = MI->isCall();
764 SU->isCommutable = MI->isCommutable();
766 // Assign the Latency field of SU using target-provided information.
767 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
778 const MCSchedClassDesc *SC = getSchedClass(SU);
784 SU->hasReservedResource = true;
787 SU->isUnbuffered = true;
797 void ScheduleDAGInstrs::collectVRegUses(SUnit *SU) {
798 const MachineInstr *MI = SU->getInstr();
814 if (UI->SU == SU)
818 VRegUses.insert(VReg2SUnit(Reg, 0, SU));
895 SUnit *SU = MISUnitMap[MI];
896 assert(SU && "No SUnit mapped to this MI");
899 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : nullptr;
903 collectVRegUses(SU);
919 addPhysRegDeps(SU, j);
923 addVRegDefDeps(SU, j);
926 addVRegUseDeps(SU, j);
935 if (SU->NumSuccs == 0 && SU->Latency > 1
937 SDep Dep(SU, SDep::Artificial);
938 Dep.setLatency(SU->Latency - 1);
958 I->second[i]->addPred(SDep(SU, SDep::Barrier));
964 SDep Dep(SU, SDep::Barrier);
969 // Add SU to the barrier chain.
971 BarrierChain->addPred(SDep(SU, SDep::Barrier));
972 BarrierChain = SU;
975 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
983 // Chain all possibly aliasing memory references through SU.
988 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
991 AliasChain = SU;
993 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
999 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1005 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1008 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
1016 // SU and barrier _could_ be reordered, they should not. In addition,
1019 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1046 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1052 I->second.push_back(SU);
1057 AliasMemDefs[V].push_back(SU);
1061 NonAliasMemDefs[V].push_back(SU);
1071 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1081 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1086 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
1089 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU, RejectMemNodes,
1105 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1108 PendingLoads.push_back(SU);
1129 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU,
1132 AliasMemUses[V].push_back(SU);
1134 NonAliasMemUses[V].push_back(SU);
1137 adjustChainDeps(AA, MFI, MF.getDataLayout(), SU, &ExitSU,
1141 addChainDependency(AAForDep, MFI, MF.getDataLayout(), SU, AliasChain,
1144 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1346 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1348 SU->getInstr()->dump();
1352 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1355 if (SU == &EntrySU)
1357 else if (SU == &ExitSU)
1360 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1407 bool isVisited(const SUnit *SU) const {
1408 return R.DFSNodeData[SU->NodeNum].SubtreeID
1414 void visitPreorder(const SUnit *SU) {
1415 R.DFSNodeData[SU->NodeNum].InstrCount =
1416 SU->getInstr()->isTransient() ? 0 : 1;
1422 void visitPostorderNode(const SUnit *SU) {
1425 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1426 RootData RData(SU->NodeNum);
1427 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1434 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1436 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1441 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1448 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1459 RootSet[SU->NodeNum] = RData;
1499 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1574 void follow(const SUnit *SU) {
1575 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1594 static bool hasDataSucc(const SUnit *SU) {
1596 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1612 const SUnit *SU = &*SI;
1613 if (Impl.isVisited(SU) || hasDataSucc(SU))
1617 Impl.visitPreorder(SU);
1618 DFS.follow(SU);