Cross Reference: /external/llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines Matching refs:SITargetLowering
39 SITargetLowering::SITargetLowering(TargetMachine &TM,
295 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
302 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
308 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
343 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
434 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
476 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
502 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
508 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
523 SITargetLowering::getPreferredVectorAction(EVT VT) const {
530 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
537 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
572 SDValue SITargetLowering::LowerFormalArguments(
875 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
887 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
898 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
906 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
925 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
951 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
997 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
1026 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1101 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1117 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1134 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1146 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1288 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1334 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1372 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1381 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1410 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1449 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1491 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1558 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1570 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1597 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1621 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1767 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1800 SDValue SITargetLowering::performAndCombine(SDNode *N,
1854 SDValue SITargetLowering::performOrCombine(SDNode *N,
1884 SDValue SITargetLowering::performClassCombine(SDNode *N,
1917 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1953 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1984 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
2163 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
2201 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
2290 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2310 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2328 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2379 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2415 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2447 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2461 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2520 SITargetLowering::ConstraintType
2521 SITargetLowering::getConstraintType(StringRef Constraint) const {