Searched defs:Imm (Results 1 - 25 of 107) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.h87 virtual bool selectVSplat(SDNode *N, APInt &Imm,
90 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
92 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
94 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
96 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
98 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
100 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
102 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
104 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
106 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons
122 getImm(const SDNode *Node, uint64_t Imm) argument
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H A DMipsAnalyzeImmediate.cpp29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument
43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument
126 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument
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H A DMipsISelDAGToDAG.cpp117 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, argument
123 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
128 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
133 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
138 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
143 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
148 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
153 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
158 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
163 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h74 inline SDValue getI32Imm(unsigned Imm, SDLoc DL) { argument
75 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
/external/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { argument
46 if (Imm == 0)
49 if (Imm.getBitWidth() <= 64) {
51 if (isInt<32>(Imm.getSExtValue()))
54 if (isUInt<32>(Imm.getZExtValue()))
57 if ((Imm.getZExtValue() & 0xffffffff) == 0)
67 const APInt &Imm, Type *Ty) {
90 if (Idx == 0 && Imm.getBitWidth() <= 64) {
95 if (isInt<16>(Imm.getSExtValue()))
100 if (Idx == 1 && Imm
66 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) argument
184 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) argument
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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp84 const ConstantFP *Imm = MO.getFPImm(); local
85 if (Imm->getType()->isFloatTy())
86 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat());
87 else if (Imm->getType()->isDoubleTy())
88 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h790 bool isLegalICmpImmediate(int64_t Imm) const override;
796 bool isLegalAddImmediate(int64_t Imm) const override;
845 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
884 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
960 void addLegalFPImmediate(const APFloat& Imm) { argument
961 LegalFPImmediates.push_back(Imm);
H A DX86FrameLowering.cpp97 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) { argument
99 if (isInt<8>(Imm))
103 if (isInt<8>(Imm))
109 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) { argument
111 if (isInt<8>(Imm))
115 if (isInt<8>(Imm))
129 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) { argument
131 if (isInt<8>(Imm))
135 if (isInt<8>(Imm))
/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp77 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { argument
80 return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
85 static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) { argument
90 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
92 Imm &= ~(0xFFFFLL << ShiftAmt);
94 return Imm | Chunk;
257 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
262 Imm &= ~(Mask << (Idx * 16));
265 Imm |= Mask << (Idx * 16);
267 return Imm;
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H A DAArch64ConditionOptimizer.cpp254 int Imm; local
257 std::tie(Imm, Opc, Cmp) = Info;
265 .addImm(Imm)
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp89 static uint32_t getIntInlineImmEncoding(IntTy Imm) { argument
90 if (Imm >= 0 && Imm <= 64)
91 return 128 + Imm;
93 if (Imm >= -16 && Imm <= -1)
94 return 192 + std::abs(Imm);
212 int64_t Imm = 0; local
215 Imm = Op.getImm();
220 OS.write((uint8_t) ((Imm >> (
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/external/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp128 uint64_t Imm = MO.isImm() ? MO.getImm() : 0; local
133 LE.write<uint32_t>(Imm >> 32);
135 BE.write<uint32_t>(Imm >> 32);
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp95 int64_t Imm = MO.getImm(); local
99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
107 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
145 int64_t Imm = MO.getImm(); local
149 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
152 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
219 int Imm = (int) MO.getImm(); local
221 if (Imm)
224 switch (Imm) {
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp264 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; local
265 return reverseBits(Imm | RegBits) >> 22;
280 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; local
281 return reverseBits(Imm | RegBits) >> 22;
296 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; local
297 return reverseBits(Imm | RegBits) >> 22;
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp74 int64_t Imm = MI->getOperand(Op).getImm(); local
75 switch (Imm) {
114 int64_t Imm = MI->getOperand(Op).getImm(); local
115 switch (Imm) {
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local
131 switch (Imm) {
H A DX86IntelInstPrinter.cpp56 int64_t Imm = MI->getOperand(Op).getImm(); local
57 switch (Imm) {
96 int64_t Imm = MI->getOperand(Op).getImm(); local
97 switch (Imm) {
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; local
113 switch (Imm) {
/external/llvm/lib/CodeGen/
H A DStackMaps.cpp103 int64_t Imm = (++MOI)->getImm(); local
105 getDwarfRegNum(Reg, TRI), Imm);
112 int64_t Imm = (++MOI)->getImm(); local
114 getDwarfRegNum(Reg, TRI), Imm);
120 int64_t Imm = MOI->getImm(); local
121 Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, Imm);
/external/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp179 // One of operands might be an Imm operand, and OpNo may refer to it after
214 APInt Imm; local
223 Imm = APInt(64, OpToFold.getImm());
235 Imm = Imm.getLoBits(32);
238 Imm = Imm.getHiBits(32);
290 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp18 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { argument
25 int32_t SImmVal = Imm.getSExtValue();
26 uint32_t ZImmVal = Imm.getZExtValue();
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonInstPrinter.cpp131 int64_t Imm; local
132 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
133 Imm = SignExtend64<9>(Imm);
135 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
136 O << formatImm(Imm/64);
141 int64_t Imm; local
142 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
143 Imm = SignExtend64<10>(Imm);
151 int64_t Imm; local
161 int64_t Imm; local
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/external/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp38 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { argument
40 return BaseT::getIntImmCost(Imm, Ty);
48 if (Imm == 0)
51 if (Imm.getBitWidth() <= 64) {
52 if (isInt<16>(Imm.getSExtValue()))
55 if (isInt<32>(Imm.getSExtValue())) {
57 if ((Imm.getZExtValue() & 0xFFFF) == 0)
67 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, argument
70 return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
85 if ((Idx == 1) && Imm
101 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp50 inline SDValue getI32Imm(unsigned Imm, SDLoc dl) { argument
51 return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
/external/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp28 enum MapKind { Operand, Imm, Reg }; enumerator in enum:__anon13301::PseudoLoweringEmitter::OpData::MapKind
32 uint64_t Imm; // Integer immedate value. member in union:__anon13301::PseudoLoweringEmitter::OpData::__anon13302
105 OperandMap[BaseIdx + i].Kind = OpData::Imm;
106 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
234 case OpData::Imm:
236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelDAGToDAG.cpp48 inline SDValue getSmallIPtrImm(unsigned Imm);
96 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) { argument
97 return CurDAG->getTargetConstant(Imm, MVT::i32);
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DSIMCCodeEmitter.cpp245 } Imm; local
248 Imm.f = MO.getFPImm();
249 Value |= ((uint64_t)Imm.i) << 32;

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