Searched defs:Op2 (Results 1 - 25 of 44) sorted by relevance

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/external/llvm/include/llvm/Target/
H A DTargetSelectionDAGInfo.h51 SDValue Op1, SDValue Op2,
68 SDValue Op1, SDValue Op2,
84 SDValue Op1, SDValue Op2,
97 SDValue Op1, SDValue Op2,
136 SDValue Op1, SDValue Op2,
49 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
66 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
82 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
95 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
134 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
/external/llvm/lib/IR/
H A DInstructions.cpp62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) { argument
63 if (Op1->getType() != Op2->getType())
/external/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp867 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local
873 Ops[5].getAsInteger(10, Op2);
874 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
903 uint32_t Op2 = Bits & 0x7; local
906 + "_c" + utostr(CRm) + "_" + utostr(Op2);
/external/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp161 MCOperand Op2 = MI.getOperand(2); local
162 assert(Op2.isImm() && "Second operand is not immediate.");
163 Encoding |= Op2.getImm() & 0xffff;
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp103 MachineOperand &Op2 = MI->getOperand(2); local
119 NewMI->addOperand(Op2);
146 MachineOperand &Op2 = MI->getOperand(2); local
157 NewMI->addOperand(Op2);
188 MachineOperand &Op2 = MI->getOperand(2); local
198 NewMI->addOperand(Op2);
225 MachineOperand &Op2 = MI->getOperand(2); local
239 NewMI->addOperand(Op2);
H A DHexagonPeephole.cpp291 MachineOperand Op2 = MI->getOperand(S2); local
292 ChangeOpInto(MI->getOperand(S1), Op2);
H A DHexagonSplitDouble.cpp701 MachineOperand &Op2 = MI->getOperand(2); local
719 if (Op2.isImm()) {
721 .addImm(Op2.getImm());
722 } else if (Op2.isReg()) {
724 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
755 MachineOperand &Op2 = MI->getOperand(2); local
756 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
757 int64_t Sh64 = Op2
879 MachineOperand &Op2 = MI->getOperand(2); local
[all...]
H A DHexagonHardwareLoops.cpp639 const MachineOperand &Op2 = CondI->getOperand(2); local
643 if (Op2.isImm() || Op1.getReg() == IVReg)
644 EndValue = &Op2;
/external/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp206 const MachineOperand *Op2 = &MI2.getOperand(N2 + X86::AddrDisp); local
207 if (!isIdenticalOp(*Op1, *Op2)) {
208 if (Op1->isImm() && Op2->isImm())
209 AddrDispShift = Op1->getImm() - Op2->getImm();
210 else if (Op1->isGlobal() && Op2->isGlobal() &&
211 Op1->getGlobal() == Op2->getGlobal())
212 AddrDispShift = Op1->getOffset() - Op2->getOffset();
/external/llvm/lib/Transforms/Utils/
H A DBuildLibCalls.cpp269 /// (e.g. 'fmin'). This function is known to take type matching 'Op1' and 'Op2'
270 /// and return one value with the same type. If 'Op1/Op2' are long double, 'l'
271 /// is added as the suffix of name, if 'Op1/Op2' is a float, we add a 'f'
273 Value *llvm::EmitBinaryFloatFnCall(Value *Op1, Value *Op2, StringRef Name, argument
280 Op1->getType(), Op2->getType(), nullptr);
281 CallInst *CI = B.CreateCall(Callee, {Op1, Op2}, Name);
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
347 unsigned Op1, Op2; local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
360 unsigned Op1, Op2; local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
366 DecodeGRRegsRegisterClass(Inst, Op2, Addres
373 unsigned Op1, Op2; local
386 unsigned Op1, Op2; local
400 unsigned Op1, Op2; local
413 unsigned Op1, Op2; local
426 unsigned Op1, Op2; local
511 unsigned Op1, Op2; local
525 unsigned Op1, Op2; local
539 unsigned Op1, Op2, Op3; local
552 unsigned Op1, Op2, Op3; local
565 unsigned Op1, Op2, Op3; local
578 unsigned Op1, Op2, Op3; local
591 unsigned Op1, Op2, Op3; local
605 unsigned Op1, Op2, Op3; local
620 unsigned Op1, Op2, Op3; local
634 unsigned Op1, Op2, Op3; local
648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local
682 unsigned Op1, Op2, Op3, Op4, Op5; local
702 unsigned Op1, Op2, Op3; local
721 unsigned Op1, Op2, Op3; local
[all...]
/external/llvm/lib/Transforms/Scalar/
H A DNaryReassociate.cpp159 // Tries to match Op1 and Op2 by using V.
160 bool matchTernaryOp(BinaryOperator *I, Value *V, Value *&Op1, Value *&Op2);
529 Value *&Op2) {
532 return match(V, m_Add(m_Value(Op1), m_Value(Op2)));
534 return match(V, m_Mul(m_Value(Op1), m_Value(Op2)));
528 matchTernaryOp(BinaryOperator *I, Value *V, Value *&Op1, Value *&Op2) argument
H A DLoopRerollPass.cpp1190 Value *Op2 = RootInst->getOperand(j); local
1196 if (Instruction *Op2I = dyn_cast<Instruction>(Op2))
1200 DenseMap<Value *, Value *>::iterator BMI = BaseMap.find(Op2);
1202 Op2 = BMI->second;
1205 if (DRS.Roots[Iter-1] == (Instruction*) Op2) {
1206 Op2 = DRS.BaseInst;
1212 if (BaseInst->getOperand(Swapped ? unsigned(!j) : j) != Op2) {
1219 BaseInst->getOperand(!j) == Op2) {
H A DScalarizer.cpp402 Scatterer Op2 = scatter(&SI, SI.getOperand(2)); local
404 assert(Op2.size() == NumElems && "Mismatched select");
412 Res[I] = Builder.CreateSelect(Op0[I], Op1[I], Op2[I],
417 Res[I] = Builder.CreateSelect(Op0, Op1[I], Op2[I],
/external/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp324 const MachineOperand &Op2 = I->getOperand(2); local
326 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
349 unsigned N = Op2.getImm();
/external/llvm/include/llvm/Analysis/
H A DScalarEvolution.h839 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument
841 SmallVector<const SCEV *, 3> Ops = {Op0, Op1, Op2};
851 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument
853 SmallVector<const SCEV *, 3> Ops = {Op0, Op1, Op2};
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h647 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, argument
653 Ops.push_back(Op2);
918 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
919 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
921 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
923 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
934 SDValue Op1, SDValue Op2);
936 SDValue Op1, SDValue Op2, SDValue Op3);
949 EVT VT2, SDValue Op1, SDValue Op2);
951 EVT VT2, SDValue Op1, SDValue Op2, SDValu
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp736 SDValue Op2 = Op.getOperand(2); local
739 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
773 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
780 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
781 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
933 SDValue Op2 = Op.getOperand(2); local
961 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
[all...]
H A DFastISel.cpp1840 bool Op1IsKill, unsigned Op2,
1847 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1853 .addReg(Op2, getKillRegState(Op2IsKill));
1858 .addReg(Op2, getKillRegState(Op2IsKill));
1837 fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
H A DLegalizeFloatTypes.cpp2032 SDValue Op2 = GetPromotedFloat(N->getOperand(2)); local
2034 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp68 const MCOperand &Op2 = MI->getOperand(2); local
73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
109 if (Op2.isImm() && Op3.isImm()) {
112 int64_t immr = Op2.getImm();
143 if (Op2.getImm() > Op3.getImm()) {
146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
161 const MCOperand &Op2 local
689 const MCOperand &Op2 = MI->getOperand(3); local
[all...]
/external/llvm/include/llvm/IR/
H A DPatternMatch.h1246 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument
1247 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument
1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
/external/llvm/lib/Analysis/
H A DCFLAliasAnalysis.cpp185 auto *Op2 = Inst.getOperand(1); local
187 Output.push_back(Edge(&Inst, Op2, EdgeType::Assign, AttrNone));
/external/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp566 const MachineOperand &Op2 = Inst.getOperand(2); local
575 if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
576 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
/external/pdfium/third_party/lcms2-2.6/src/
H A Dcmsopt.c139 cmsBool _Remove2Op(cmsPipeline* Lut, cmsStageSignature Op1, cmsStageSignature Op2) argument
153 if ((*pt1) ->Implements == Op1 && (*pt2) ->Implements == Op2) {

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