/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 105 MachineOperand &Op4 = MI->getOperand(4); local 114 NewMI->addOperand(Op4); 147 MachineOperand &Op4 = MI->getOperand(4); // Modifier value. local 151 Hexagon::C6)->addOperand(Op4); 189 MachineOperand &Op4 = MI->getOperand(4); // Modifier value. local 192 Hexagon::C6)->addOperand(Op4);
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/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); 657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 682 unsigned Op1, Op2, Op3, Op4, Op5; local 687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); 692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); local 708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 722 unsigned Op4 local [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 1243 SDValue Op4 = Node->getOperand(4); local 1244 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2988 SDValue Op0, Op1, Op2, Op3, Op4; local 3000 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) 3009 OutOps.push_back(Op4);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 5773 SDValue Op3, SDValue Op4) { 5774 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 5780 SDValue Op3, SDValue Op4, SDValue Op5) { 5781 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 5772 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 5779 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 3874 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); local 3876 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { 3878 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4.getImm()); 3895 return Error(Op4.getStartLoc(), 3907 return Error(Op4.getStartLoc(), 3917 NewOp4, Op4.getStartLoc(), Op4.getEndLoc(), getContext()); 3938 AArch64Operand &Op4 = static_cast<AArch64Operand &>(*Operands[4]); local 3940 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { 3942 const MCConstantExpr *Op4CE = dyn_cast<MCConstantExpr>(Op4 [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5405 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); local 5406 if (!Op3.isReg() || !Op4.isReg()) 5410 auto Op4Reg = Op4.getReg(); 5445 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially 5454 LastOp = &Op4; 5475 std::swap(Op4, Op5);
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