Searched defs:Reads (Results 1 - 5 of 5) sorted by relevance
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBundle.h | 154 /// Reads - One of the operands read the virtual register. This does not 156 bool Reads; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo
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/external/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.h | 70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence 118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may 126 /// that mapped the itinerary class to the variant Writes or Reads. 133 IdxVec Reads; member in struct:llvm::CodeGenSchedClass 149 makeArrayRef(Reads) == R; 359 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const; 372 ArrayRef<unsigned> Reads) const; 417 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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H A D | SubtargetEmitter.cpp | 866 IdxVec Reads = SCI->Reads; local 881 Reads.clear(); 883 Writes, Reads); 894 Writes, Reads); 975 for (unsigned UseIdx = 0, EndIdx = Reads.size(); 978 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
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/external/llvm/lib/CodeGen/ |
H A D | EarlyIfConversion.cpp | 274 SmallVector<unsigned, 8> Reads; local 300 Reads.push_back(Reg); 303 while (!Reads.empty()) 304 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
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H A D | RegisterCoalescer.cpp | 1183 bool Reads, Writes; local 1184 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); 1188 if (DstInt && !Reads && SubIdx) 1189 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI)); 1199 MO.setIsUndef(!Reads);
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