Searched defs:Reads (Results 1 - 5 of 5) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h154 /// Reads - One of the operands read the virtual register. This does not
156 bool Reads; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo
/external/llvm/utils/TableGen/
H A DCodeGenSchedule.h70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
133 IdxVec Reads; member in struct:llvm::CodeGenSchedClass
149 makeArrayRef(Reads) == R;
359 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
372 ArrayRef<unsigned> Reads) const;
417 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
H A DSubtargetEmitter.cpp866 IdxVec Reads = SCI->Reads; local
881 Reads.clear();
883 Writes, Reads);
894 Writes, Reads);
975 for (unsigned UseIdx = 0, EndIdx = Reads.size();
978 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
/external/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp274 SmallVector<unsigned, 8> Reads; local
300 Reads.push_back(Reg);
303 while (!Reads.empty())
304 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
H A DRegisterCoalescer.cpp1183 bool Reads, Writes; local
1184 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1188 if (DstInt && !Reads && SubIdx)
1189 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
1199 MO.setIsUndef(!Reads);

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