| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 60 StoreToOffset(TR, SP, offset.Int32Value());
114 void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { function in class:art::arm64::Arm64Assembler
136 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value());
155 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value());
172 StoreToOffset(scratch.AsXRegister(), TR, offs.Int32Value());
181 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value());
195 StoreToOffset(source.AsXRegister(), SP, dest_off.Int32Value());
197 StoreToOffset(scratch.AsXRegister(), SP, dest_off.Int32Value() + 8);
363 StoreToOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value());
372 StoreToOffset(scratc
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| /art/compiler/utils/arm/ |
| H A D | assembler_arm32.cc | 1544 void Arm32Assembler::StoreToOffset(StoreOperandType type, function in class:art::arm::Arm32Assembler
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| H A D | assembler_thumb2.cc | 3733 void Thumb2Assembler::StoreToOffset(StoreOperandType type, function in class:art::arm::Thumb2Assembler
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 2366 void MipsAssembler::StoreToOffset(StoreOperandType type, Register reg, Register base, function in class:art::mips::MipsAssembler
2452 StoreToOffset(kStoreWord, RA, SP, stack_offset);
2457 StoreToOffset(kStoreWord, reg, SP, stack_offset);
2462 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0);
2472 StoreToOffset(kStoreWord, reg.AsCoreRegister(), SP, offset);
2537 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
2540 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value());
2541 StoreToOffset(kStoreWord, src.AsRegisterPairHigh(),
2556 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value());
2562 StoreToOffset(kStoreWor
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 1906 void Mips64Assembler::StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, function in class:art::mips64::Mips64Assembler
1991 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset);
1996 StoreToOffset(kStoreDoubleword, reg, SP, stack_offset);
2001 StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0);
2017 StoreToOffset((size == 4) ? kStoreWord : kStoreDoubleword,
2074 StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value());
2076 StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value());
2095 StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value());
2101 StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value());
2109 StoreToOffset(kStoreWor
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