/art/test/003-omnibus-opcodes/src/ |
H A D | FloatMath.java | 339 static void jlmTests(float ff, double dd) { argument 347 Main.assertTrue(approxEqual(Math.abs(dd), dd, 0.001)); 348 Main.assertTrue(approxEqual(Math.abs(-dd), dd, 0.001)); 349 Main.assertTrue(approxEqual(Math.min(dd, -5.0), -5.0, 0.001)); 350 Main.assertTrue(approxEqual(Math.max(dd, -5.0), dd, 0.001)); 352 double sq = Math.sqrt(dd); 353 Main.assertTrue(approxEqual(sq*sq, dd, 0.00 [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_thumb2.h | 205 void vmovd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE; 209 bool vmovd(DRegister dd, double d_imm, Condition cond = AL) OVERRIDE; 213 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE; 214 void vstrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE; 217 void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; 219 void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; 221 void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; 223 void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; 225 void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; 227 void vdivd(DRegister dd, DRegiste 517 LoadDoubleLiteral(uint32_t location, DRegister dd, Size size = kLongOrFPLiteral1KiB) argument 613 Fixup(Register rn, Register rt2, SRegister sd, DRegister dd, Condition cond, Type type, Size size, uint32_t location) argument [all...] |
H A D | assembler_arm32.cc | 343 void Arm32Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) { argument 344 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); 363 bool Arm32Assembler::vmovd(DRegister dd, double d_imm, Condition cond) { argument 371 dd, D0, D0); 384 void Arm32Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm, argument 386 EmitVFPddd(cond, B21 | B20, dd, dn, dm); 396 void Arm32Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm, argument 398 EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm); 408 void Arm32Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm, argument 410 EmitVFPddd(cond, B21, dd, d 420 vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument 432 vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument 444 vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument 455 vabsd(DRegister dd, DRegister dm, Condition cond) argument 465 vnegd(DRegister dd, DRegister dm, Condition cond) argument 474 vsqrtd(DRegister dd, DRegister dm, Condition cond) argument 484 vcvtds(DRegister dd, SRegister sm, Condition cond) argument 504 vcvtdi(DRegister dd, SRegister sm, Condition cond) argument 524 vcvtdu(DRegister dd, SRegister sm, Condition cond) argument 534 vcmpd(DRegister dd, DRegister dm, Condition cond) argument 544 vcmpdz(DRegister dd, Condition cond) argument 1062 vldrd(DRegister dd, const Address& ad, Condition cond) argument 1075 vstrd(DRegister dd, const Address& ad, Condition cond) argument 1153 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument 1186 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument [all...] |
H A D | assembler_thumb2.cc | 438 inline int32_t Thumb2Assembler::VldrdEncoding32(DRegister dd, Register rn, int32_t offset) { argument 444 ((static_cast<int32_t>(dd) & 0x10) << (22 - 4)) | // Move D from bit 4 to bit 22. 445 ((static_cast<int32_t>(dd) & 0x0f) << (12 - 0)) | // Move Vd from bits 0-3 to bits 12-15. 941 bool Thumb2Assembler::vmovd(DRegister dd, double d_imm, Condition cond) { argument 949 dd, D0, D0); 961 void Thumb2Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) { argument 962 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); 972 void Thumb2Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm, argument 974 EmitVFPddd(cond, B21 | B20, dd, dn, dm); 984 void Thumb2Assembler::vsubd(DRegister dd, DRegiste argument 996 vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument 1008 vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument 1020 vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument 1032 vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument 1043 vabsd(DRegister dd, DRegister dm, Condition cond) argument 1053 vnegd(DRegister dd, DRegister dm, Condition cond) argument 1062 vsqrtd(DRegister dd, DRegister dm, Condition cond) argument 1072 vcvtds(DRegister dd, SRegister sm, Condition cond) argument 1092 vcvtdi(DRegister dd, SRegister sm, Condition cond) argument 1112 vcvtdu(DRegister dd, SRegister sm, Condition cond) argument 1122 vcmpd(DRegister dd, DRegister dm, Condition cond) argument 1132 vcmpdz(DRegister dd, Condition cond) argument 2971 vldrd(DRegister dd, const Address& ad, Condition cond) argument 2984 vstrd(DRegister dd, const Address& ad, Condition cond) argument 3062 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument 3095 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument 3480 LoadLiteral(DRegister dd, Literal* literal) argument [all...] |