| /art/compiler/jni/quick/x86/ |
| H A D | calling_convention_x86.cc | 131 ManagedRegister in_reg = CurrentParamRegister(); local
133 if (!in_reg.IsNoRegister()) {
136 ManagedRegisterSpill spill(in_reg, size, spill_offset);
140 in_reg = CurrentParamHighLongRegister();
141 DCHECK(!in_reg.IsNoRegister());
143 ManagedRegisterSpill spill2(in_reg, size, spill_offset + 4);
|
| /art/compiler/jni/quick/x86_64/ |
| H A D | calling_convention_x86_64.cc | 110 ManagedRegister in_reg = CurrentParamRegister(); local
111 if (!in_reg.IsNoRegister()) {
114 ManagedRegisterSpill spill(in_reg, size, spill_offset);
|
| /art/compiler/jni/quick/ |
| H A D | jni_compiler.cc | 55 ManagedRegister in_reg);
175 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); local
176 __ VerifyObject(in_reg, mr_conv->IsCurrentArgPossiblyNull());
177 __ StoreRef(handle_scope_offset, in_reg);
532 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); local
535 __ CreateHandleScopeEntry(out_reg, handle_scope_offset, in_reg, null_allowed);
539 __ Move(out_reg, in_reg, mr_conv->CurrentParamSize());
569 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); local
574 // TODO: recycle value in in_reg rather than reload from handle scope
582 __ Store(out_off, in_reg, param_siz
593 SetNativeParameter(Assembler* jni_asm, JniCallingConvention* jni_conv, ManagedRegister in_reg) argument
[all...] |
| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 553 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); local
555 CHECK(in_reg.IsNoRegister() || in_reg.IsXRegister()) << in_reg;
561 if (in_reg.IsNoRegister()) {
564 in_reg = out_reg;
566 ___ Cmp(reg_w(in_reg.AsOverlappingWRegister()), 0);
567 if (!out_reg.Equals(in_reg)) {
598 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); local
600 CHECK(in_reg
[all...] |
| /art/compiler/optimizing/ |
| H A D | intrinsics_arm.cc | 303 Register in_reg = in.AsRegister<Register>(); local
306 __ Asr(mask, in_reg, 31);
307 __ add(out_reg, in_reg, ShifterOperand(mask));
|
| H A D | intrinsics_arm64.cc | 416 FPRegister in_reg = is64bit ? DRegisterFrom(in) : SRegisterFrom(in); local
419 __ Fabs(out_reg, in_reg);
452 Register in_reg = is64bit ? XRegisterFrom(in) : WRegisterFrom(in); local
455 __ Cmp(in_reg, Operand(0));
456 __ Cneg(out_reg, in_reg, lt);
634 FPRegister in_reg = is_double ? local
639 FPRegister temp1_reg = temps.AcquireSameSizeAs(in_reg);
647 __ Fadd(temp1_reg, in_reg, temp1_reg);
|
| /art/compiler/utils/x86/ |
| H A D | assembler_x86.cc | 2290 X86ManagedRegister in_reg = min_reg.AsX86(); local
2291 CHECK(in_reg.IsCpuRegister());
2293 VerifyObject(in_reg, null_allowed);
2296 if (!out_reg.Equals(in_reg)) {
2299 testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
2331 X86ManagedRegister in_reg = min_reg.AsX86(); local
2333 CHECK(in_reg.IsCpuRegister());
2335 if (!out_reg.Equals(in_reg)) {
2338 testl(in_reg
[all...] |
| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64.cc | 3042 X86_64ManagedRegister in_reg = min_reg.AsX86_64(); local
3043 if (in_reg.IsNoRegister()) { // TODO(64): && null_allowed
3045 in_reg = out_reg;
3047 movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3049 CHECK(in_reg.IsCpuRegister());
3051 VerifyObject(in_reg, null_allowed);
3054 if (!out_reg.Equals(in_reg)) {
3057 testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
3089 X86_64ManagedRegister in_reg local
[all...] |
| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 2782 MipsManagedRegister in_reg = min_reg.AsMips(); local
2783 CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg;
2790 if (in_reg.IsNoRegister()) {
2793 in_reg = out_reg;
2795 if (!out_reg.Equals(in_reg)) {
2798 Beqz(in_reg.AsCoreRegister(), &null_arg);
2831 MipsManagedRegister in_reg = min_reg.AsMips(); local
2833 CHECK(in_reg
[all...] |
| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 2333 Mips64ManagedRegister in_reg = min_reg.AsMips64(); local
2334 CHECK(in_reg.IsNoRegister() || in_reg.IsGpuRegister()) << in_reg;
2341 if (in_reg.IsNoRegister()) {
2344 in_reg = out_reg;
2346 if (!out_reg.Equals(in_reg)) {
2349 Beqzc(in_reg.AsGpuRegister(), &null_arg);
2383 Mips64ManagedRegister in_reg = min_reg.AsMips64(); local
2385 CHECK(in_reg
[all...] |