/art/runtime/arch/arm64/ |
H A D | memcmp16_arm64.S | 45 #define mask x13 define 79 mov mask, #~0 80 lsl mask, mask, limit 81 bic data1, data1, mask 82 bic data2, data2, mask 93 // Create a 16b mask 94 mov mask, #0xFFFF 99 and data1, data1, mask 100 and data2, data2, mask [all...] |
/art/runtime/ |
H A D | type_lookup_table.h | 135 uint32_t mask = static_cast<uint16_t>(~GetSizeMask()); local 136 return (hash & mask) == (data & mask);
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H A D | type_lookup_table.cc | 29 static uint16_t MakeData(uint16_t class_def_idx, uint32_t hash, uint32_t mask) { argument 30 uint16_t hash_mask = static_cast<uint16_t>(~mask);
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H A D | dex_file_verifier_test.cc | 333 static void SetMethodFlags(DexFile* dex_file, const char* method, uint32_t mask) { argument 338 uint8_t base1 = static_cast<uint8_t>(mask & 0x7F); 340 mask >>= 7; 342 uint8_t base2 = static_cast<uint8_t>(mask & 0x7F); 344 mask >>= 7; 346 uint8_t base3 = static_cast<uint8_t>(mask & 0x7F); 356 // Apply the given mask to method flags. 357 static void ApplyMaskToMethodFlags(DexFile* dex_file, const char* method, uint32_t mask) { argument 359 value &= mask; 363 // Apply the given mask t 364 OrMaskToMethodFlags(DexFile* dex_file, const char* method, uint32_t mask) argument 506 uint32_t mask = ((i & 1) != 0 ? kAccPrivate : 0) | local 642 uint32_t mask = ((j & 1) != 0 ? kAccPrivate : 0) | local 734 ApplyMaskShifted(uint32_t src_value, uint32_t mask) argument 939 SetFieldFlags(DexFile* dex_file, const char* field, uint32_t mask) argument 963 ApplyMaskToFieldFlags(DexFile* dex_file, const char* field, uint32_t mask) argument 970 OrMaskToFieldFlags(DexFile* dex_file, const char* field, uint32_t mask) argument [all...] |
H A D | art_method.h | 347 constexpr uint32_t mask = kAccFastNative | kAccNative; local 348 return (GetAccessFlags() & mask) == mask;
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H A D | mem_map.cc | 91 // mask = 0000111111111110000 112 constexpr uintptr_t mask = mask_ones & ~(kPageSize - 1); local 115 return (input & mask) + LOW_MEM_START;
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H A D | stack_map.h | 589 // Compute the size of the live register bit mask (in bytes), for a 834 ALWAYS_INLINE void SetRegisterMask(const StackMapEncoding& encoding, uint32_t mask) { argument 835 encoding.GetRegisterMaskEncoding().Store(region_, mask);
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/art/disassembler/ |
H A D | disassembler_mips.cc | 30 uint32_t mask; member in struct:art::mips::MipsInstruction 36 return (instruction & mask) == value;
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H A D | disassembler_arm.cc | 1871 uint32_t mask = opB; local 1876 size_t count = 3 - CTZ(mask); 1880 bool positive_mask = ((mask & (1 << (3 - i))) != 0);
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/art/runtime/gc/accounting/ |
H A D | space_bitmap-inl.h | 38 const uintptr_t mask = OffsetToMask(offset); local 45 if ((old_word & mask) != 0) { 49 } while (!atomic_entry->CompareExchangeWeakRelaxed(old_word, old_word | mask)); 165 const uintptr_t mask = OffsetToMask(offset); local 175 if ((old_word & mask) == 0) { 176 *address = old_word | mask; 179 *address = old_word & ~mask; 182 return (old_word & mask) != 0;
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/art/runtime/verifier/ |
H A D | register_line.h | 400 uint32_t mask = 1 << depth; local 402 if ((pair.second & mask) != 0) { 404 pair.second ^= mask;
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/art/test/564-checker-negbitwise/src/ |
H A D | Main.java | 79 public static int $opt$noinline$notAnd(int base, int mask) { argument 81 return base & ~mask; 129 public static long $opt$noinline$notOr(long base, long mask) { argument 131 return base | ~mask; 176 public static int $opt$noinline$notXor(int base, int mask) { argument 178 return base ^ ~mask; 212 public static int $opt$noinline$notAndConstant(int mask) { argument 214 return 0xf & ~mask; 268 public static int $opt$noinline$notAndMultipleUses(int base, int mask) { argument 270 int tmp = ~mask; [all...] |
/art/sigchainlib/ |
H A D | sigchain.cc | 153 sigset_t mask, old_mask; local 154 sigfillset(&mask); 155 sigprocmask(SIG_BLOCK, &mask, &old_mask); 282 // Don't allow claimed signals in the mask. If a signal chain has been claimed
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/art/compiler/optimizing/ |
H A D | code_generator.h | 231 uint32_t mask = 0; local 233 mask |= (1 << registers[i]); 235 return mask;
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H A D | instruction_simplifier.cc | 242 int64_t mask = (input_other->GetType() == Primitive::kPrimLong) local 245 if ((cst & mask) == 0) { 962 // Eliminate And from UShr+And if the And-mask contains all the bits that 963 // can be non-zero after UShr. Transform Shr+And to UShr if the And-mask
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H A D | intrinsics_arm.cc | 287 Register mask = locations->GetTemp(0).AsRegister<Register>(); local 297 __ Asr(mask, in_reg_hi, 31); 298 __ adds(out_reg_lo, in_reg_lo, ShifterOperand(mask)); 299 __ adc(out_reg_hi, in_reg_hi, ShifterOperand(mask)); 300 __ eor(out_reg_lo, mask, ShifterOperand(out_reg_lo)); 301 __ eor(out_reg_hi, mask, ShifterOperand(out_reg_hi)); 306 __ Asr(mask, in_reg, 31); 307 __ add(out_reg, in_reg, ShifterOperand(mask)); 308 __ eor(out_reg, mask, ShifterOperand(out_reg));
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H A D | intrinsics_x86.cc | 2292 static void SwapBits(Register reg, Register temp, int32_t shift, int32_t mask, argument 2295 Immediate imm_mask(mask);
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H A D | intrinsics_x86_64.cc | 204 locations->AddTemp(Location::RequiresFpuRegister()); // FP reg to hold mask. 216 // TODO: Can mask directly with constant area using pand if we can guarantee 256 CpuRegister mask = locations->GetTemp(0).AsRegister<CpuRegister>(); local 259 // Create mask. 260 __ movq(mask, out); 261 __ sarq(mask, Immediate(63)); 262 // Add mask. 263 __ addq(out, mask); 264 __ xorq(out, mask); 266 // Create mask 2308 SwapBits(CpuRegister reg, CpuRegister temp, int32_t shift, int32_t mask, X86_64Assembler* assembler) argument 2352 SwapBits64(CpuRegister reg, CpuRegister temp, CpuRegister temp_mask, int32_t shift, int64_t mask, X86_64Assembler* assembler) argument [all...] |
H A D | code_generator_x86.cc | 2109 XmmRegister mask = locations->GetTemp(1).AsFpuRegister<XmmRegister>(); local 2111 // 0x80000000 (mask for bit 31, representing the sign of a 2114 __ movd(mask, constant); 2115 __ xorps(out.AsFpuRegister<XmmRegister>(), mask); 2121 XmmRegister mask = locations->GetTemp(0).AsFpuRegister<XmmRegister>(); local 2123 // 0x8000000000000000 (mask for bit 63, representing the sign of 2125 __ LoadLongConstant(mask, INT64_C(0x8000000000000000)); 2126 __ xorpd(out.AsFpuRegister<XmmRegister>(), mask); 2151 XmmRegister mask = locations->GetTemp(0).AsFpuRegister<XmmRegister>(); local 2153 __ movss(mask, codegen [all...] |
H A D | code_generator_x86_64.cc | 2305 XmmRegister mask = locations->GetTemp(0).AsFpuRegister<XmmRegister>(); local 2307 // 0x80000000 (mask for bit 31, representing the sign of a 2309 __ movss(mask, codegen_->LiteralInt32Address(0x80000000)); 2310 __ xorps(out.AsFpuRegister<XmmRegister>(), mask); 2316 XmmRegister mask = locations->GetTemp(0).AsFpuRegister<XmmRegister>(); local 2318 // 0x8000000000000000 (mask for bit 63, representing the sign of 2320 __ movsd(mask, codegen_->LiteralInt64Address(INT64_C(0x8000000000000000))); 2321 __ xorpd(out.AsFpuRegister<XmmRegister>(), mask);
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/art/compiler/utils/arm/ |
H A D | assembler_thumb2.cc | 3138 // Convert the given IT state to a mask bit given bit 0 of the first 3173 uint8_t mask = ToItMask(i1, firstcond0, 3); local 3177 mask |= ToItMask(i2, firstcond0, 2); 3180 mask |= ToItMask(i3, firstcond0, 1); 3183 mask |= 1U /* 0b0001 */; 3194 mask;
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