Searched defs:ori (Results 1 - 9 of 9) sorted by relevance

/external/llvm/test/MC/PowerPC/
H A Dppc64-fixup-apply.s30 ori 1, 1, target5+0x8000@l label
/external/jmonkeyengine/engine/src/test/jme3test/bullet/
H A DTestBrickWall.java187 public void addBrick(Vector3f ori) { argument
191 reBoxg.setLocalTranslation(ori);
H A DTestBrickTower.java214 public void addBrick(Vector3f ori) { argument
217 reBoxg.setLocalTranslation(ori);
H A DTestWalkingChar.java186 private void addBrick(Vector3f ori) { argument
189 reBoxg.setLocalTranslation(ori);
/external/jmonkeyengine/engine/src/test/jme3test/batching/
H A DTestBatchNodeTower.java228 public void addBrick(Vector3f ori) { argument
231 reBoxg.setLocalTranslation(ori);
/external/skia/src/views/
H A DSkStackViewLayout.cpp20 void SkStackViewLayout::setOrient(Orient ori) argument
22 SkASSERT((unsigned)ori < kOrientCount);
23 fOrient = SkToU8(ori);
/external/v8/src/mips/
H A Dassembler-mips.cc182 // specially coded on MIPS means that it is a lui/ori instruction, and that is
1689 void Assembler::ori(Register rt, Register rs, int32_t j) { function in class:v8::Assembler
1786 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
3102 ori(at, at, (imm32 & kImm16Mask));
3130 // Interpret 2 instructions generated by li: lui/ori
3152 // On Mips, a target address is stored in a lui/ori instruction pair, each
3187 // Must use 2 instructions to insure patchable code => just use lui and ori.
3189 // ori rt rt, lower-16.
/external/v8/src/ppc/
H A Dassembler-ppc.cc143 // coded. Being specially coded on PPC means that it is a lis/ori
324 // This code assumes a FIXED_SEQUENCE for 64bit loads (lis/ori)
329 // 618c0000 ori r12, r12, 0
332 // 618ccd40 ori r12, r12, 52544
338 // This code assumes a FIXED_SEQUENCE for 32bit loads (lis/ori)
342 // 618c5000 ori r12, r12, 20480
462 instr = ORI; // nop: ori, 0,0,0
475 instr = ORI; // nop: ori, 0,0,0
980 void Assembler::ori(Register ra, Register rs, const Operand& imm) { function in class:v8::internal::Assembler
1665 ori(ds
[all...]
/external/v8/src/mips64/
H A Dassembler-mips64.cc160 // specially coded on MIPS means that it is a lui/ori instruction, and that is
1772 void Assembler::ori(Register rt, Register rs, int32_t j) { function in class:v8::internal::Assembler
1948 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
3405 // 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
3407 // 3: ori(rd, rd, j.imm32_ & kImm16Mask);
3409 // Patching the address must replace all the lui & ori instructions,
3438 // ori rt, rt, lower-16.
3440 // ori rt rt, lower-16.

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