| /art/compiler/utils/arm/ |
| H A D | assembler_arm.h | 444 virtual void and_(Register rd, Register rn, const ShifterOperand& so,
447 virtual void ands(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { argument
448 and_(rd, rn, so, cond, kCcSet);
451 virtual void eor(Register rd, Register rn, const ShifterOperand& so,
454 virtual void eors(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { argument
455 eor(rd, rn, so, cond, kCcSet);
458 virtual void sub(Register rd, Register rn, const ShifterOperand& so,
461 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { argument
462 sub(rd, rn, so, cond, kCcSet);
465 virtual void rsb(Register rd, Registe
468 rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
475 adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
482 adcs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
489 sbcs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
496 rscs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
513 orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
520 orns(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
527 movs(Register rd, const ShifterOperand& so, Condition cond = AL) argument
534 bics(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
541 mvns(Register rd, const ShifterOperand& so, Condition cond = AL) argument
727 AddConstantSetFlags(Register rd, Register rn, int32_t value, Condition cond = AL) argument
730 AddConstant(Register rd, int32_t value, Condition cond = AL, SetCc set_cc = kCcDontCare) argument
822 Lsls(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument
829 Lsrs(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument
836 Asrs(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument
843 Rors(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument
850 Rrxs(Register rd, Register rm, Condition cond = AL) argument
857 Lsls(Register rd, Register rm, Register rn, Condition cond = AL) argument
864 Lsrs(Register rd, Register rm, Register rn, Condition cond = AL) argument
871 Asrs(Register rd, Register rm, Register rn, Condition cond = AL) argument
878 Rors(Register rd, Register rm, Register rn, Condition cond = AL) argument
890 ShifterOperandCanHold(Register rd, Register rn, Opcode opcode, uint32_t immediate, ShifterOperand* shifter_op) argument
[all...] |
| H A D | assembler_arm32.cc | 56 bool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
65 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, argument
67 EmitType01(cond, so.type(), AND, set_cc, rn, rd, so);
71 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, argument
73 EmitType01(cond, so.type(), EOR, set_cc, rn, rd, so);
77 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, argument
79 EmitType01(cond, so.type(), SUB, set_cc, rn, rd, so);
82 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, argument
84 EmitType01(cond, so.type(), RSB, set_cc, rn, rd, so);
87 void Arm32Assembler::add(Register rd, Registe argument
93 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
99 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
105 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
133 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
148 mov(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
154 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
160 mvn(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
166 mul(Register rd, Register rn, Register rm, Condition cond) argument
172 mla(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
179 mls(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
200 sdiv(Register rd, Register rn, Register rm, Condition cond) argument
216 udiv(Register rd, Register rn, Register rm, Condition cond) argument
232 sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
251 ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
270 ldr(Register rd, const Address& ad, Condition cond) argument
275 str(Register rd, const Address& ad, Condition cond) argument
280 ldrb(Register rd, const Address& ad, Condition cond) argument
285 strb(Register rd, const Address& ad, Condition cond) argument
290 ldrh(Register rd, const Address& ad, Condition cond) argument
295 strh(Register rd, const Address& ad, Condition cond) argument
300 ldrsb(Register rd, const Address& ad, Condition cond) argument
305 ldrsh(Register rd, const Address& ad, Condition cond) argument
310 ldrd(Register rd, const Address& ad, Condition cond) argument
316 strd(Register rd, const Address& ad, Condition cond) argument
573 EmitType01(Condition cond, int type, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
602 EmitMemOp(Condition cond, bool load, bool byte, Register rd, const Address& ad) argument
641 EmitMemOpAddressMode3(Condition cond, int32_t mode, Register rd, const Address& ad) argument
674 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
691 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
721 clz(Register rd, Register rm, Condition cond) argument
735 movw(Register rd, uint16_t imm16, Condition cond) argument
744 movt(Register rd, uint16_t imm16, Condition cond) argument
767 EmitReverseBytes(Register rd, Register rm, Condition cond, uint8_t op1, uint8_t op2) argument
782 rbit(Register rd, Register rm, Condition cond) argument
796 rev(Register rd, Register rm, Condition cond) argument
801 rev16(Register rd, Register rm, Condition cond) argument
806 revsh(Register rd, Register rm, Condition cond) argument
811 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument
864 strex(Register rd, Register rt, Register rn, Condition cond) argument
882 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
1201 Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
1208 Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
1216 Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
1224 Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
1230 Rrx(Register rd, Register rm, Condition cond, SetCc set_cc) argument
1235 Lsl(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
1241 Lsr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
1247 Asr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
1253 Ror(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
1302 Push(Register rd, Condition cond) argument
1307 Pop(Register rd, Condition cond) argument
1322 Mov(Register rd, Register rm, Condition cond) argument
1398 AddConstant(Register rd, Register rn, int32_t value, Condition cond, SetCc set_cc) argument
1449 LoadImmediate(Register rd, int32_t value, Condition cond) argument
[all...] |
| H A D | assembler_thumb2.cc | 383 inline int32_t Thumb2Assembler::MovwEncoding32(Register rd, int32_t value) { argument
386 (static_cast<int32_t>(rd) << 8) |
393 inline int32_t Thumb2Assembler::MovtEncoding32(Register rd, int32_t value) { argument
395 int32_t movw_encoding = MovwEncoding32(rd, (value >> 16) & 0xffff);
399 inline int32_t Thumb2Assembler::MovModImmEncoding32(Register rd, int32_t value) { argument
403 (static_cast<int32_t>(rd) << 8) | static_cast<int32_t>(mod_imm);
478 inline int16_t Thumb2Assembler::AdrEncoding16(Register rd, int32_t offset) { argument
481 DCHECK(!IsHighRegister(rd));
482 return B15 | B13 | (rd << 8) | (offset >> 2);
485 inline int32_t Thumb2Assembler::AdrEncoding32(Register rd, int32_ argument
542 and_(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
548 eor(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
554 sub(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
560 rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
566 add(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
572 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
578 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
584 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
612 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
618 orn(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
624 mov(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
630 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
636 mvn(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
642 mul(Register rd, Register rn, Register rm, Condition cond) argument
667 mla(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
685 mls(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
739 sdiv(Register rd, Register rn, Register rm, Condition cond) argument
756 udiv(Register rd, Register rn, Register rm, Condition cond) argument
773 sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
794 ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
815 ldr(Register rd, const Address& ad, Condition cond) argument
820 str(Register rd, const Address& ad, Condition cond) argument
825 ldrb(Register rd, const Address& ad, Condition cond) argument
830 strb(Register rd, const Address& ad, Condition cond) argument
835 ldrh(Register rd, const Address& ad, Condition cond) argument
840 strh(Register rd, const Address& ad, Condition cond) argument
845 ldrsb(Register rd, const Address& ad, Condition cond) argument
850 ldrsh(Register rd, const Address& ad, Condition cond) argument
855 ldrd(Register rd, const Address& ad, Condition cond) argument
860 ldrd(Register rd, Register rd2, const Address& ad, Condition cond) argument
872 strd(Register rd, const Address& ad, Condition cond) argument
877 strd(Register rd, Register rd2, const Address& ad, Condition cond) argument
1175 Is32BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1338 Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1425 Emit16BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1616 Emit16BitAddSub(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1776 EmitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1792 EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, Condition cond, SetCc set_cc) argument
1837 EmitShift(Register rd, Register rn, Shift shift, Register rm, Condition cond, SetCc set_cc) argument
2314 EmitLoadStore(Condition cond, bool load, bool byte, bool half, bool is_signed, Register rd, const Address& ad) argument
2615 clz(Register rd, Register rm, Condition cond) argument
2629 movw(Register rd, uint16_t imm16, Condition cond) argument
2647 movt(Register rd, uint16_t imm16, Condition cond) argument
2665 rbit(Register rd, Register rm, Condition cond) argument
2682 EmitReverseBytes(Register rd, Register rm, uint32_t op) argument
2707 rev(Register rd, Register rm, Condition cond) argument
2713 rev16(Register rd, Register rm, Condition cond) argument
2719 revsh(Register rd, Register rm, Condition cond) argument
2745 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument
2781 strex(Register rd, Register rt, Register rn, Condition cond) argument
2789 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
3245 Push(Register rd, Condition cond) argument
3250 Pop(Register rd, Condition cond) argument
3265 Mov(Register rd, Register rm, Condition cond) argument
3277 Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3285 Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3294 Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3303 Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3311 Rrx(Register rd, Register rm, Condition cond, SetCc set_cc) argument
3317 Lsl(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3324 Lsr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3331 Asr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3338 Ror(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3492 AddConstant(Register rd, Register rn, int32_t value, Condition cond, SetCc set_cc) argument
3562 LoadImmediate(Register rd, int32_t value, Condition cond) argument
[all...] |
| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.cc | 77 void Arm64Assembler::AddConstant(XRegister rd, int32_t value, Condition cond) { argument
78 AddConstant(rd, rd, value, cond);
81 void Arm64Assembler::AddConstant(XRegister rd, XRegister rn, int32_t value, argument
85 ___ Add(reg_x(rd), reg_x(rn), value);
87 // temp = rd + value
88 // rd = cond ? temp : rn
90 temps.Exclude(reg_x(rd), reg_x(rn));
93 ___ Csel(reg_x(rd), temp, reg_x(rd), con
[all...] |
| /art/compiler/utils/mips/ |
| H A D | assembler_mips.cc | 125 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument
128 CHECK_NE(rd, kNoRegister);
132 static_cast<uint32_t>(rd) << kRdShift |
186 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { argument
187 EmitR(0, rs, rt, rd, 0, 0x21);
194 void MipsAssembler::Subu(Register rd, Register rs, Register rt) { argument
195 EmitR(0, rs, rt, rd, 0, 0x23);
218 void MipsAssembler::MulR2(Register rd, Register rs, Register rt) { argument
220 EmitR(0x1c, rs, rt, rd, 0, 2);
223 void MipsAssembler::DivR2(Register rd, Registe argument
229 ModR2(Register rd, Register rs, Register rt) argument
235 DivuR2(Register rd, Register rs, Register rt) argument
241 ModuR2(Register rd, Register rs, Register rt) argument
247 MulR6(Register rd, Register rs, Register rt) argument
252 MuhR6(Register rd, Register rs, Register rt) argument
257 MuhuR6(Register rd, Register rs, Register rt) argument
262 DivR6(Register rd, Register rs, Register rt) argument
267 ModR6(Register rd, Register rs, Register rt) argument
272 DivuR6(Register rd, Register rs, Register rt) argument
277 ModuR6(Register rd, Register rs, Register rt) argument
282 And(Register rd, Register rs, Register rt) argument
290 Or(Register rd, Register rs, Register rt) argument
298 Xor(Register rd, Register rs, Register rt) argument
306 Nor(Register rd, Register rs, Register rt) argument
310 Movz(Register rd, Register rs, Register rt) argument
315 Movn(Register rd, Register rs, Register rt) argument
320 Seleqz(Register rd, Register rs, Register rt) argument
325 Selnez(Register rd, Register rs, Register rt) argument
330 ClzR6(Register rd, Register rs) argument
335 ClzR2(Register rd, Register rs) argument
340 CloR6(Register rd, Register rs) argument
345 CloR2(Register rd, Register rs) argument
350 Seb(Register rd, Register rt) argument
354 Seh(Register rd, Register rt) argument
358 Wsbh(Register rd, Register rt) argument
362 Bitswap(Register rd, Register rt) argument
367 Sll(Register rd, Register rt, int shamt) argument
372 Srl(Register rd, Register rt, int shamt) argument
377 Rotr(Register rd, Register rt, int shamt) argument
382 Sra(Register rd, Register rt, int shamt) argument
387 Sllv(Register rd, Register rt, Register rs) argument
391 Srlv(Register rd, Register rt, Register rs) argument
395 Rotrv(Register rd, Register rt, Register rs) argument
399 Srav(Register rd, Register rt, Register rs) argument
403 Ext(Register rd, Register rt, int pos, int size) argument
410 Ins(Register rd, Register rt, int pos, int size) argument
456 Mfhi(Register rd) argument
461 Mflo(Register rd) argument
510 Slt(Register rd, Register rs, Register rt) argument
514 Sltu(Register rd, Register rs, Register rt) argument
590 Jalr(Register rd, Register rs) argument
1148 Movf(Register rd, Register rs, int cc) argument
1154 Movt(Register rd, Register rs, int cc) argument
1331 Move(Register rd, Register rs) argument
1335 Clear(Register rd) argument
1339 Not(Register rd, Register rs) argument
1348 Pop(Register rd) argument
1353 PopAndReturn(Register rd, Register rt) argument
1359 LoadConst32(Register rd, int32_t value) argument
1442 LoadDConst64(FRegister rd, int64_t value, Register temp) argument
[all...] |
| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.cc | 91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, argument
95 CHECK_NE(rd, kNoGpuRegister);
99 static_cast<uint32_t>(rd) << kRdShift |
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, argument
108 CHECK_NE(rd, kNoGpuRegister);
112 static_cast<uint32_t>(rd) << kRdShift |
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, argument
121 CHECK_NE(rd, kNoGpuRegister);
125 static_cast<uint32_t>(rd) << kRdShift |
179 void Mips64Assembler::Addu(GpuRegister rd, GpuRegiste argument
187 Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
195 Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
199 Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
203 MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
207 MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
211 DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
215 ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
219 DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
223 ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
227 Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
231 Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
235 Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
239 Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
243 Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
247 Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
251 And(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
259 Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
267 Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
275 Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
279 Bitswap(GpuRegister rd, GpuRegister rt) argument
283 Dbitswap(GpuRegister rd, GpuRegister rt) argument
287 Seb(GpuRegister rd, GpuRegister rt) argument
291 Seh(GpuRegister rd, GpuRegister rt) argument
295 Dsbh(GpuRegister rd, GpuRegister rt) argument
299 Dshd(GpuRegister rd, GpuRegister rt) argument
316 Wsbh(GpuRegister rd, GpuRegister rt) argument
340 Sll(GpuRegister rd, GpuRegister rt, int shamt) argument
344 Srl(GpuRegister rd, GpuRegister rt, int shamt) argument
348 Rotr(GpuRegister rd, GpuRegister rt, int shamt) argument
352 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument
356 Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
360 Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
364 Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
368 Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
372 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument
376 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument
380 Drotr(GpuRegister rd, GpuRegister rt, int shamt) argument
384 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument
388 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument
392 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument
396 Drotr32(GpuRegister rd, GpuRegister rt, int shamt) argument
400 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument
404 Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
408 Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
412 Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
416 Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
481 Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
485 Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
497 Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
501 Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
505 Clz(GpuRegister rd, GpuRegister rs) argument
509 Clo(GpuRegister rd, GpuRegister rs) argument
513 Dclz(GpuRegister rd, GpuRegister rs) argument
517 Dclo(GpuRegister rd, GpuRegister rs) argument
521 Jalr(GpuRegister rd, GpuRegister rs) argument
1023 Move(GpuRegister rd, GpuRegister rs) argument
1027 Clear(GpuRegister rd) argument
1031 Not(GpuRegister rd, GpuRegister rs) argument
1035 LoadConst32(GpuRegister rd, int32_t value) argument
1049 LoadConst64(GpuRegister rd, int64_t value) argument
[all...] |
| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64_test.cc | 55 std::random_device rd; local
56 std::default_random_engine e1(rd());
|
| /art/disassembler/ |
| H A D | disassembler_mips.cc | 66 { kRTypeMask | (0x1f << 11), 9 | (31 << 11), "jalr", "S", }, // rd = 31 is implicit.
67 { kRTypeMask | (0x1f << 11), 9, "jr", "S", }, // rd = 0 is implicit.
416 uint32_t rd = (instruction >> 11) & 0x1f; // R-type. local
459 case 'D': args << 'r' << rd; break; local
460 case 'd': args << 'f' << rd; break; local
530 case 'Z': args << (rd + 1); break; // sz ([d]ext size).
531 case 'z': args << (rd - sa + 1); break; // sz ([d]ins size).
|