Searched defs:reg3 (Results 1 - 20 of 20) sorted by relevance

/external/v8/test/unittests/interpreter/
H A Dbytecode-register-allocator-unittest.cc204 Register reg3 = allocator.NextConsecutiveRegister(); local
207 CHECK(Register::AreContiguous(reg0, reg1, reg2, reg3));
/external/libvpx/libvpx/vpx_dsp/mips/
H A Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
51 DOTP_CONST_PAIR(reg5, reg3, cospi_12_64, cospi_20_64, reg5, reg3);
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
67 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3);
77 reg5 = reg7 + reg3;
78 reg7 = reg7 - reg3;
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
359 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
439 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
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H A Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
49 DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1);
50 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5);
52 loc1 = reg15 + reg3;
53 reg3 = reg15 - reg3;
85 DOTP_CONST_PAIR(reg3, reg1
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
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/external/v8/src/interpreter/
H A Dbytecodes.cc907 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, argument
912 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) {
915 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) {
/external/vixl/src/vixl/a64/
H A Dmacro-assembler-a64.cc2455 const Register& reg3,
2458 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
2468 const FPRegister& reg3,
2470 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
2487 const Register& reg3,
2489 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
2496 const FPRegister& reg3,
2498 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit();
2505 const CPURegister& reg3,
2510 const CPURegister regs[] = {reg1, reg2, reg3, reg
2453 Include(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2466 Include(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2485 Exclude(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2494 Exclude(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2503 Exclude(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) argument
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/external/v8/src/full-codegen/arm64/
H A Dfull-codegen-arm64.cc3620 Register reg3) {
3622 __ Push(reg1, reg2, reg3);
3619 PushOperands(Register reg1, Register reg2, Register reg3) argument
/external/v8/src/full-codegen/mips/
H A Dfull-codegen-mips.cc1873 Register reg3) {
1875 __ Push(reg1, reg2, reg3);
1879 Register reg3, Register reg4) {
1881 __ Push(reg1, reg2, reg3, reg4);
1872 PushOperands(Register reg1, Register reg2, Register reg3) argument
1878 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/v8/src/full-codegen/mips64/
H A Dfull-codegen-mips64.cc1874 Register reg3) {
1876 __ Push(reg1, reg2, reg3);
1880 Register reg3, Register reg4) {
1882 __ Push(reg1, reg2, reg3, reg4);
1873 PushOperands(Register reg1, Register reg2, Register reg3) argument
1879 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/v8/src/full-codegen/ppc/
H A Dfull-codegen-ppc.cc1840 Register reg3) {
1842 __ Push(reg1, reg2, reg3);
1846 Register reg3, Register reg4) {
1848 __ Push(reg1, reg2, reg3, reg4);
1839 PushOperands(Register reg1, Register reg2, Register reg3) argument
1845 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/v8/src/full-codegen/s390/
H A Dfull-codegen-s390.cc1798 Register reg3) {
1800 __ Push(reg1, reg2, reg3);
1804 Register reg3, Register reg4) {
1806 __ Push(reg1, reg2, reg3, reg4);
1797 PushOperands(Register reg1, Register reg2, Register reg3) argument
1803 PushOperands(Register reg1, Register reg2, Register reg3, Register reg4) argument
/external/v8/src/arm64/
H A Dassembler-arm64.cc208 Register reg3, Register reg4) {
209 CPURegList regs(reg1, reg2, reg3, reg4);
223 const CPURegister& reg3, const CPURegister& reg4,
232 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
260 const CPURegister& reg3, const CPURegister& reg4,
266 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
207 GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4) argument
222 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
259 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
/external/v8/src/ia32/
H A Dmacro-assembler-ia32.cc3144 Register reg3,
3151 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
3157 if (reg3.is_valid()) regs |= reg3.bit();
3142 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
/external/v8/src/mips64/
H A Dmacro-assembler-mips64.cc7119 Register reg3,
7126 if (reg3.is_valid()) regs |= reg3.bit();
7176 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4,
7179 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
7187 if (reg3.is_valid()) regs |= reg3.bit();
7117 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
/external/v8/src/s390/
H A Dmacro-assembler-s390.cc3688 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, argument
3694 if (reg3.is_valid()) regs |= reg3.bit();
5438 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4,
5441 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
5449 if (reg3.is_valid()) regs |= reg3.bit();
/external/v8/src/x87/
H A Dmacro-assembler-x87.cc2991 Register reg3,
2998 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
3004 if (reg3.is_valid()) regs |= reg3.bit();
2989 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
/external/v8/src/mips/
H A Dmacro-assembler-mips.cc6781 Register reg3,
6788 if (reg3.is_valid()) regs |= reg3.bit();
6838 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4,
6841 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
6849 if (reg3.is_valid()) regs |= reg3.bit();
6779 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
/external/v8/src/ppc/
H A Dmacro-assembler-ppc.cc4733 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, argument
4739 if (reg3.is_valid()) regs |= reg3.bit();
4794 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4,
4797 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
4805 if (reg3.is_valid()) regs |= reg3.bit();
/external/v8/src/x64/
H A Dmacro-assembler-x64.cc5454 Register reg3,
5461 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
5467 if (reg3.is_valid()) regs |= reg3.bit();
5452 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
/external/sqlite/dist/orig/
H A Dsqlite3.c93770 int reg1, reg2, reg3; local
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/external/sqlite/dist/
H A Dsqlite3.c93788 int reg1, reg2, reg3; local
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