Searched defs:reg_id (Results 1 - 13 of 13) sorted by relevance

/art/compiler/utils/mips64/
H A Dmanaged_register_mips64.h101 explicit Mips64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} argument
103 static Mips64ManagedRegister FromRegId(int reg_id) { argument
104 Mips64ManagedRegister reg(reg_id);
/art/compiler/utils/arm64/
H A Dmanaged_register_arm64.h205 explicit Arm64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} argument
207 static Arm64ManagedRegister FromRegId(int reg_id) { argument
208 Arm64ManagedRegister reg(reg_id);
/art/compiler/utils/
H A Dmanaged_register.h78 explicit ManagedRegister(int reg_id) : id_(reg_id) { } argument
/art/compiler/utils/arm/
H A Dmanaged_register_arm.h254 explicit ArmManagedRegister(int reg_id) : ManagedRegister(reg_id) {} argument
256 static ArmManagedRegister FromRegId(int reg_id) { argument
257 ArmManagedRegister reg(reg_id);
/art/compiler/utils/mips/
H A Dmanaged_register_mips.h208 explicit MipsManagedRegister(int reg_id) : ManagedRegister(reg_id) {} argument
210 static MipsManagedRegister FromRegId(int reg_id) { argument
211 MipsManagedRegister reg(reg_id);
/art/compiler/utils/x86/
H A Dmanaged_register_x86.h205 explicit X86ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} argument
207 static X86ManagedRegister FromRegId(int reg_id) { argument
208 X86ManagedRegister reg(reg_id);
/art/compiler/utils/x86_64/
H A Dmanaged_register_x86_64.h191 explicit X86_64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} argument
193 static X86_64ManagedRegister FromRegId(int reg_id) { argument
194 X86_64ManagedRegister reg(reg_id);
/art/compiler/optimizing/
H A Dcode_generator_mips64.cc929 size_t CodeGeneratorMIPS64::SaveCoreRegister(size_t stack_index, uint32_t reg_id) { argument
930 __ StoreToOffset(kStoreDoubleword, GpuRegister(reg_id), SP, stack_index);
934 size_t CodeGeneratorMIPS64::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) { argument
935 __ LoadFromOffset(kLoadDoubleword, GpuRegister(reg_id), SP, stack_index);
939 size_t CodeGeneratorMIPS64::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
940 __ StoreFpuToOffset(kStoreDoubleword, FpuRegister(reg_id), SP, stack_index);
944 size_t CodeGeneratorMIPS64::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
945 __ LoadFpuFromOffset(kLoadDoubleword, FpuRegister(reg_id), SP, stack_index);
H A Dcode_generator_arm64.cc1124 size_t CodeGeneratorARM64::SaveCoreRegister(size_t stack_index, uint32_t reg_id) { argument
1125 Register reg = Register(VIXLRegCodeFromART(reg_id), kXRegSize);
1130 size_t CodeGeneratorARM64::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) { argument
1131 Register reg = Register(VIXLRegCodeFromART(reg_id), kXRegSize);
1136 size_t CodeGeneratorARM64::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
1137 FPRegister reg = FPRegister(reg_id, kDRegSize);
1142 size_t CodeGeneratorARM64::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
1143 FPRegister reg = FPRegister(reg_id, kDRegSize);
H A Dcode_generator_mips.cc1036 size_t CodeGeneratorMIPS::SaveCoreRegister(size_t stack_index, uint32_t reg_id) { argument
1037 __ StoreToOffset(kStoreWord, Register(reg_id), SP, stack_index);
1041 size_t CodeGeneratorMIPS::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) { argument
1042 __ LoadFromOffset(kLoadWord, Register(reg_id), SP, stack_index);
1046 size_t CodeGeneratorMIPS::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
1047 __ StoreDToOffset(FRegister(reg_id), SP, stack_index);
1051 size_t CodeGeneratorMIPS::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
1052 __ LoadDFromOffset(FRegister(reg_id), SP, stack_index);
H A Dcode_generator_arm.cc742 size_t CodeGeneratorARM::SaveCoreRegister(size_t stack_index, uint32_t reg_id) { argument
743 __ StoreToOffset(kStoreWord, static_cast<Register>(reg_id), SP, stack_index);
747 size_t CodeGeneratorARM::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) { argument
748 __ LoadFromOffset(kLoadWord, static_cast<Register>(reg_id), SP, stack_index);
752 size_t CodeGeneratorARM::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
753 __ StoreSToOffset(static_cast<SRegister>(reg_id), SP, stack_index);
757 size_t CodeGeneratorARM::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
758 __ LoadSFromOffset(static_cast<SRegister>(reg_id), SP, stack_index);
H A Dcode_generator_x86.cc741 size_t CodeGeneratorX86::SaveCoreRegister(size_t stack_index, uint32_t reg_id) { argument
742 __ movl(Address(ESP, stack_index), static_cast<Register>(reg_id));
746 size_t CodeGeneratorX86::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) { argument
747 __ movl(static_cast<Register>(reg_id), Address(ESP, stack_index));
751 size_t CodeGeneratorX86::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
752 __ movsd(Address(ESP, stack_index), XmmRegister(reg_id));
756 size_t CodeGeneratorX86::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
757 __ movsd(XmmRegister(reg_id), Address(ESP, stack_index));
H A Dcode_generator_x86_64.cc949 size_t CodeGeneratorX86_64::SaveCoreRegister(size_t stack_index, uint32_t reg_id) { argument
950 __ movq(Address(CpuRegister(RSP), stack_index), CpuRegister(reg_id));
954 size_t CodeGeneratorX86_64::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) { argument
955 __ movq(CpuRegister(reg_id), Address(CpuRegister(RSP), stack_index));
959 size_t CodeGeneratorX86_64::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
960 __ movsd(Address(CpuRegister(RSP), stack_index), XmmRegister(reg_id));
964 size_t CodeGeneratorX86_64::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) { argument
965 __ movsd(XmmRegister(reg_id), Address(CpuRegister(RSP), stack_index));

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