Search

Home

Sort by

Searched defs:rm (Results 1 - 7 of 7) sorted by relevance

/art/compiler/utils/x86/
H A D	assembler_x86.h	57 Register rm() const { function in class:art::x86::Operand 798 inline void EmitRegisterOperand(int rm, int reg); 799 inline void EmitXmmRegisterOperand(int rm, XmmRegister reg); 803 void EmitOperand(int rm, const Operand& operand); 805 void EmitComplex(int rm, const Operand& operand, const Immediate& immediate); 810 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm); 811 void EmitGenericShift(int rm, const Operand& operand, Register shifter); 826 inline void X86Assembler::EmitRegisterOperand(int rm, int reg) { argument 827 CHECK_GE(rm, 0); 828 CHECK_LT(rm, 832 EmitXmmRegisterOperand(int rm, XmmRegister reg) argument [all...]
/art/compiler/utils/x86_64/
H A D	assembler_x86_64.h	65 Register rm() const { function in class:art::x86_64::Operand 871 void EmitRegisterOperand(uint8_t rm, uint8_t reg); 872 void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg); 876 void EmitOperand(uint8_t rm, const Operand& operand); 878 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate); 883 void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm); 884 void EmitGenericShift(bool wide, int rm, CpuRegister operand, CpuRegister shifter); 934 inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { argument 935 CHECK_GE(rm, 0); 936 CHECK_LT(rm, 940 EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) argument [all...]
/art/disassembler/
H A D	disassembler_x86.cc	160 std::string DisassemblerX86::DumpAddress(uint8_t mod, uint8_t rm, uint8_t rex64, uint8_t rex_w, argument 166 if (mod == 0 && rm == 5) { 174 } else if (rm == 4 && mod != 3) { // SIB 227 DumpRmReg(address, rex_w, rm, byte_operand \|\| byte_second_operand, 232 DumpBaseReg(address, rex64, rm); 296 const char* opcode3 = ""; // Mod-rm part. 298 bool store = false; // stores to memory (ie rm is on the left) 299 bool load = false; // loads from memory (ie rm is on the right) 1300 uint8_t rm = modrm & 7; local 1301 std::string address = DumpAddress(mod, rm, rex6 [all...]
H A D	disassembler_arm.cc	154 explicit RmLslImm2(uint32_t instr) : imm2((instr >> 4) & 0x3), rm(instr & 0xf) {} 156 ArmRegister rm; member in struct:art::arm::RmLslImm2 159 os << r.rm; 1436 unpred = unpred \|\| (Rm.rm.r == SP) \|\| (Rm.rm.r == PC); 1616 ThumbRegister rm(instr, 3); 1625 args << Rd << ", " << rm << ", #" << imm5; 1679 ThumbRegister rm(instr, 3); 1682 args << rdn << ", " << rm; local 1691 ArmRegister rm(inst 1695 args << DN_Rdn << ", " << rm; local 1706 args << DN_Rdn << ", " << rm; local 1716 args << N_Rn << ", " << rm; local 1724 args << rm; local [all...]
/art/compiler/utils/arm/
H A D	assembler_arm.h	131 explicit ShifterOperand(Register rm) : type_(kRegister), rm_(rm), rs_(kNoRegister), argument 140 ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), argument 146 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), argument 276 Address(Register rn, Register rm, Mode am = Offset) : rn_(rn), rm_(rm), offset_(0), argument 278 CHECK_NE(rm, PC); 281 Address(Register rn, Register rm, Shif argument 822 Lsls(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument 829 Lsrs(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument 836 Asrs(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument 843 Rors(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) argument 850 Rrxs(Register rd, Register rm, Condition cond = AL) argument 857 Lsls(Register rd, Register rm, Register rn, Condition cond = AL) argument 864 Lsrs(Register rd, Register rm, Register rn, Condition cond = AL) argument 871 Asrs(Register rd, Register rm, Register rn, Condition cond = AL) argument 878 Rors(Register rd, Register rm, Register rn, Condition cond = AL) argument [all...]
H A D	assembler_arm32.cc	166 void Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { argument 167 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 168 EmitMulOp(cond, 0, R0, rd, rn, rm); 172 void Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra, argument 174 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 175 EmitMulOp(cond, B21, ra, rd, rn, rm); 179 void Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra, argument 181 // Assembler registers rd, rn, rm, r 186 smull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 193 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 200 sdiv(Register rd, Register rn, Register rm, Condition cond) argument 216 udiv(Register rd, Register rn, Register rm, Condition cond) argument 674 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument 691 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument 721 clz(Register rd, Register rm, Condition cond) argument 767 EmitReverseBytes(Register rd, Register rm, Condition cond, uint8_t op1, uint8_t op2) argument 782 rbit(Register rd, Register rm, Condition cond) argument 796 rev(Register rd, Register rm, Condition cond) argument 801 rev16(Register rd, Register rm, Condition cond) argument 806 revsh(Register rd, Register rm, Condition cond) argument 811 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument 1201 Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 1208 Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 1216 Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 1224 Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 1230 Rrx(Register rd, Register rm, Condition cond, SetCc set_cc) argument 1235 Lsl(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument 1241 Lsr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument 1247 Asr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument 1253 Ror(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument 1282 blx(Register rm, Condition cond) argument 1292 bx(Register rm, Condition cond) argument 1322 Mov(Register rd, Register rm, Condition cond) argument [all...]
H A D	assembler_thumb2.cc	377 inline int16_t Thumb2Assembler::AddRdnRmEncoding16(Register rdn, Register rm) { argument 378 // The high bit of rn is moved across 4-bit rm. 379 return B14 \| B10 \| (static_cast<int32_t>(rm) << 3) \| 642 void Thumb2Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { argument 645 if (rd == rm && !IsHighRegister(rd) && !IsHighRegister(rn) && !force_32bit_) { 660 static_cast<uint32_t>(rm); 667 void Thumb2Assembler::mla(Register rd, Register rn, Register rm, Register ra, argument 679 static_cast<uint32_t>(rm); 685 void Thumb2Assembler::mls(Register rd, Register rn, Register rm, Register ra, argument 697 static_cast<uint32_t>(rm); 703 smull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 721 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 739 sdiv(Register rd, Register rn, Register rm, Condition cond) argument 756 udiv(Register rd, Register rn, Register rm, Condition cond) argument 1645 Register rm = so.GetRegister(); local 1718 Register rm = so.GetRegister(); local 1792 EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, Condition cond, SetCc set_cc) argument 1837 EmitShift(Register rd, Register rn, Shift shift, Register rm, Condition cond, SetCc set_cc) argument 2615 clz(Register rd, Register rm, Condition cond) argument 2665 rbit(Register rd, Register rm, Condition cond) argument 2682 EmitReverseBytes(Register rd, Register rm, uint32_t op) argument 2707 rev(Register rd, Register rm, Condition cond) argument 2713 rev16(Register rd, Register rm, Condition cond) argument 2719 revsh(Register rd, Register rm, Condition cond) argument 3229 blx(Register rm, Condition cond) argument 3237 bx(Register rm, Condition cond) argument 3265 Mov(Register rd, Register rm, Condition cond) argument 3277 Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 3285 Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 3294 Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 3303 Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument 3311 Rrx(Register rd, Register rm, Condition cond, SetCc set_cc) argument 3317 Lsl(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument 3324 Lsr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument 3331 Asr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument 3338 Ror(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument [all...]

Completed in 79 milliseconds