Searched defs:so (Results 1 - 4 of 4) sorted by relevance

/art/compiler/utils/arm/
H A Dassembler_arm.h444 virtual void and_(Register rd, Register rn, const ShifterOperand& so,
447 virtual void ands(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { argument
448 and_(rd, rn, so, cond, kCcSet);
451 virtual void eor(Register rd, Register rn, const ShifterOperand& so,
454 virtual void eors(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { argument
455 eor(rd, rn, so, cond, kCcSet);
458 virtual void sub(Register rd, Register rn, const ShifterOperand& so,
461 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { argument
462 sub(rd, rn, so, cond, kCcSet);
465 virtual void rsb(Register rd, Register rn, const ShifterOperand& so,
468 rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
475 adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
482 adcs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
489 sbcs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
496 rscs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
513 orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
520 orns(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
527 movs(Register rd, const ShifterOperand& so, Condition cond = AL) argument
534 bics(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) argument
541 mvns(Register rd, const ShifterOperand& so, Condition cond = AL) argument
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H A Dassembler_arm32.cc65 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, argument
67 EmitType01(cond, so.type(), AND, set_cc, rn, rd, so);
71 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, argument
73 EmitType01(cond, so.type(), EOR, set_cc, rn, rd, so);
77 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, argument
79 EmitType01(cond, so.type(), SUB, set_cc, rn, rd, so);
82 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, argument
87 add(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
93 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
99 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
105 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
111 tst(Register rn, const ShifterOperand& so, Condition cond) argument
117 teq(Register rn, const ShifterOperand& so, Condition cond) argument
123 cmp(Register rn, const ShifterOperand& so, Condition cond) argument
128 cmn(Register rn, const ShifterOperand& so, Condition cond) argument
133 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
148 mov(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
154 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
160 mvn(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
573 EmitType01(Condition cond, int type, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
674 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
691 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
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H A Dassembler_thumb2.cc169 // so recalculate all load literals. This makes up for the fact that we don't mark
210 // Process fixups in reverse order so that we don't repeatedly move the same data.
282 // Ensure that the label was tracked, so that it will have the right position.
542 void Thumb2Assembler::and_(Register rd, Register rn, const ShifterOperand& so, argument
544 EmitDataProcessing(cond, AND, set_cc, rn, rd, so);
548 void Thumb2Assembler::eor(Register rd, Register rn, const ShifterOperand& so, argument
550 EmitDataProcessing(cond, EOR, set_cc, rn, rd, so);
554 void Thumb2Assembler::sub(Register rd, Register rn, const ShifterOperand& so, argument
556 EmitDataProcessing(cond, SUB, set_cc, rn, rd, so);
560 void Thumb2Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, argument
566 add(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
572 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
578 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
584 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
590 tst(Register rn, const ShifterOperand& so, Condition cond) argument
596 teq(Register rn, const ShifterOperand& so, Condition cond) argument
602 cmp(Register rn, const ShifterOperand& so, Condition cond) argument
607 cmn(Register rn, const ShifterOperand& so, Condition cond) argument
612 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
618 orn(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
624 mov(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
630 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
636 mvn(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
1175 Is32BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1338 Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1425 Emit16BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1616 Emit16BitAddSub(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1776 EmitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
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/art/compiler/optimizing/
H A Dcode_generator_arm.cc168 // We're moving two locations to locations that could overlap, so we need a parallel
298 // We're moving two locations to locations that could overlap, so we need a parallel
541 // (as it is not a callee-save register), so we can freely
568 // overlap, so we need a parallel move resolver.
1141 // No conflict possible, so just do the moves.
1324 // Must be equal high, so compare the lows.
1339 // Must be equal high, so compare the lows.
3136 // so map all rotations to a +ve. equivalent in that range.
3317 // ARM doesn't mask the shift count so we need to do it ourselves.
3735 // Ensure `out_lo` is different from `addr`, so tha
3990 ShifterOperand so; local
5848 ShifterOperand so; local
5869 ShifterOperand so; local
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