Searched refs:AsCoreRegister (Results 1 - 9 of 9) sorted by relevance
/art/compiler/utils/arm/ |
H A D | assembler_arm.cc | 394 CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister()); 401 core_spill_mask |= 1 << reg.AsArm().AsCoreRegister(); 432 StoreToOffset(kStoreWord, reg.AsCoreRegister(), SP, offset); 454 core_spill_mask |= 1 << reg.AsArm().AsCoreRegister(); 495 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 512 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 518 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 525 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 526 LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value()); 527 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S [all...] |
H A D | managed_register_arm.cc | 79 os << "Core: " << static_cast<int>(AsCoreRegister());
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H A D | managed_register_arm.h | 88 Register AsCoreRegister() const { function in class:art::arm::ArmManagedRegister 128 return FromRegId(AllocIdLow()).AsCoreRegister(); 134 return FromRegId(AllocIdHigh()).AsCoreRegister();
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H A D | managed_register_arm_test.cc | 37 EXPECT_EQ(R0, reg.AsCoreRegister()); 46 EXPECT_EQ(R1, reg.AsCoreRegister()); 55 EXPECT_EQ(R8, reg.AsCoreRegister()); 64 EXPECT_EQ(R15, reg.AsCoreRegister());
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H A D | assembler_arm32.cc | 1615 CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12);
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H A D | assembler_thumb2.cc | 3820 CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12);
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/art/compiler/utils/mips/ |
H A D | managed_register_mips.h | 90 Register AsCoreRegister() const { function in class:art::mips::MipsManagedRegister 120 return FromRegId(AllocIdLow()).AsCoreRegister(); 126 return FromRegId(AllocIdHigh()).AsCoreRegister();
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H A D | assembler_mips.cc | 2352 LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset); 2456 Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister(); 2462 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0); 2472 StoreToOffset(kStoreWord, reg.AsCoreRegister(), SP, offset); 2493 Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister(); 2537 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 2556 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 2562 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); 2569 LoadConst32(scratch.AsCoreRegister(), imm); 2570 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S [all...] |
H A D | managed_register_mips.cc | 80 os << "Core: " << static_cast<int>(AsCoreRegister());
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